est: fix layer selection for chips with different technologies

Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>

Author: eder-matheus

src/est/src/EstimateParasitics.tcl

@@ -234,10 +234,17 @@ proc parse_wire_rc_chips { keys_var flags_var selector_var } {
   return $target_chips
 }
 
-# Layer lookups use the targeted chips' technology when one is selected.
+# Layer lookups use the targeted chips' technology when one is selected;
+# layers cannot be resolved for chips with different technologies.
 proc wire_rc_tech { chips } {
   if { [llength $chips] > 0 } {
     set tech [[lindex $chips 0] getTech]
+    foreach chip $chips {
+      if { [$chip getTech] != $tech } {
+        utl::error EST 32 "-layer and -layers require chips that share one\
+          technology; set each chip separately with -chip."
+      }
+    }
     if { $tech != "NULL" } {
       return $tech
     }
@@ -491,7 +498,8 @@ proc check_parasitics { } {
 
 proc dblayer_wire_rc { layer } {
   set layer_width_dbu [$layer getWidth]
-  set layer_width_micron [ord::dbu_to_microns $layer_width_dbu]
+  set dbu_per_micron [[$layer getTech] getDbUnitsPerMicron]
+  set layer_width_micron [expr { double($layer_width_dbu) / $dbu_per_micron }]
   set res_ohm_per_sq [$layer getResistance]
   set res_ohm_per_micron [expr $res_ohm_per_sq / $layer_width_micron]
   set cap_area_pf_per_sq_micron [$layer getCapacitance]
@@ -509,7 +517,8 @@ proc dblayer_wire_rc { layer } {
 proc set_dblayer_wire_rc { layer res cap } {
   # Zero the edge cap and just use the user given value
   $layer setEdgeCapacitance 0
-  set wire_width [ord::dbu_to_microns [$layer getWidth]]
+  set dbu_per_micron [[$layer getTech] getDbUnitsPerMicron]
+  set wire_width [expr { double([$layer getWidth]) / $dbu_per_micron }]
   # Convert wire capacitance/wire_length to capacitance/area (pF/um)
   set cap_per_square [expr $cap * 1e+6 / $wire_width]
   $layer setCapacitance $cap_per_square

src/est/test/set_wire_rc_chip.ok

@@ -11,6 +11,8 @@ EST-0028
 [WARNING EST-0030] no chip uses technology no_such_tech; values ignored.
 [WARNING EST-0031] design has no RDL chip; values ignored.
 [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias
+[ERROR EST-0032] -layer and -layers require chips that share one technology; set each chip separately with -chip.
+EST-0032
 Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
 Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
 Path Group: clk

src/est/test/set_wire_rc_chip.tcl

@@ -20,6 +20,19 @@ set_wire_rc -redistribution_layer -resistance 1e-3 -capacitance 1e-1
 # a second tech makes the database multi-tech; tech-targeted values still work
 read_lef -tech -tech_name tech2 Nangate45/Nangate45.lef
 
+# a second chip on its own technology: -chip, -tech and RDL selectors succeed
+set db [ord::get_db]
+odb::dbChip_create $db [$db findTech tech2] "chip2" "RDL"
+set_wire_rc -chip chip2 -resistance 1e-3 -capacitance 1e-1
+set_wire_rc -tech tech2 -layer metal3
+set_wire_rc -redistribution_layer -resistance 2e-3 -capacitance 2e-1
+
+# heterogeneous RDL technologies cannot resolve a shared layer
+odb::dbChip_create $db [$db findTech Nangate45] "chip3" "RDL"
+set_wire_rc -redistribution_layer -resistance 2e-3 -capacitance 2e-1
+catch { set_wire_rc -redistribution_layer -layer metal3 } msg
+puts $msg
+
 # same wire RC values as make_parasitics1
 set lambda .12
 # kohm/square.