Merge remote-tracking branch 'private/master' into dpl-dpo-load-macro-flipping

Author: gudeh

BUILD.bazel

@@ -666,6 +666,7 @@ sh_binary(
         "$(rootpath @buildifier_prebuilt//:buildifier)",
         "$(rootpath //bazel:bzl_lint_test.sh)",
         "$(rootpath @buildifier_prebuilt//:buildifier)",
+        "$(rootpath @git)",
     ],
     data = [
         "MODULE.bazel",
@@ -677,5 +678,6 @@ sh_binary(
         "//bazel:tclfmt",
         "//bazel:tclint",
         "@buildifier_prebuilt//:buildifier",
+        "@git",
     ],
 )

MODULE.bazel

@@ -159,6 +159,12 @@ archive_override(
 
 bazel_dep(name = "yosys", version = "0.62.bcr.2", dev_dependency = True)
 bazel_dep(name = "yosys-slang", version = "0.0.0", dev_dependency = True)
+archive_override(
+    module_name = "yosys-slang",
+    sha256 = "34198f2ed7b2d3175c3ce3c9fb1c6c91f28dbcfe531d97b91d6b12c48431bdef",
+    strip_prefix = "sv-elab-6760afa2c9b9ba231a9c6a9e94f0939dd39f0a20",
+    urls = ["https://github.com/povik/yosys-slang/archive/6760afa2c9b9ba231a9c6a9e94f0939dd39f0a20.tar.gz"],
+)
 
 # --- Extensions ---
 

MODULE.bazel.lock

@@ -6,17 +6,27 @@
 # that file-discovery logic is not duplicated (DRY).
 set -euo pipefail
 
+TCL_TIDY_SH="$1"
+TCLFMT="$2"
+TCL_LINT_SH="$3"
+TCLINT="$4"
+BZL_TIDY_SH="$5"
+BZL_FMT_BUILDIFIER="$6"
+BZL_LINT_SH="$7"
+BZL_LINT_BUILDIFIER="$8"
+GIT="$9"
+
 export BUILD_WORKSPACE_DIRECTORY="${BUILD_WORKSPACE_DIRECTORY:-$PWD}"
 
 # TCL: auto-format then lint
-"$1" "$2"
-"$3" "$4" || rc=$?
+"${TCL_TIDY_SH}" "${TCLFMT}"
+"${TCL_LINT_SH}" "${TCLINT}" "${GIT}" || rc=$?
 
 # Bazel: auto-format then lint
-"$5" "$6"
-"$7" "$8" || rc=$?
+"${BZL_TIDY_SH}" "${BZL_FMT_BUILDIFIER}"
+"${BZL_LINT_SH}" "${BZL_LINT_BUILDIFIER}" "${GIT}" || rc=$?
 
-git -C "$BUILD_WORKSPACE_DIRECTORY" status
+"${GIT}" -C "$BUILD_WORKSPACE_DIRECTORY" status
 
 if [ "${rc:-0}" -ne 0 ]; then
     echo "Error: lint violations remain that require manual fixes." >&2

bazel/fix_lint.sh

@@ -190,7 +190,7 @@ bool Design::isSequential(odb::dbMaster* master)
   if (!lib_cell) {
     return false;
   }
-  return lib_cell->hasSequentials();
+  return lib_cell->isSequential();
 }
 
 bool Design::isInClock(odb::dbInst* inst)

src/Design.cc

@@ -582,7 +582,7 @@ bool LatencyBalancer::propagateClock(odb::dbITerm* input)
     return true;
   }
   // Combinational components
-  if (!libertyCell->hasSequentials()) {
+  if (!libertyCell->isSequential()) {
     return true;
   }
   sta::LibertyPort* inputPort

src/cts/src/LatencyBalancer.cpp

@@ -78,7 +78,7 @@ static bool IsCombinational(sta::LibertyCell* cell)
     return false;
   }
   return (!cell->isClockGate() && !cell->isPad() && !cell->isMacro()
-          && !cell->hasSequentials() && !cell->isLevelShifter()
+          && !cell->isSequential() && !cell->isLevelShifter()
           && !cell->isIsolationCell() && !cell->isMemory());
 }
 

src/cut/src/abc_library_factory.cpp

@@ -95,7 +95,7 @@ bool Blif::writeBlif(const char* file_name, bool write_arrival_requireds)
     auto master_name = master->getName();
 
     std::string current_gate
-        = ((cell->hasSequentials()) ? ".mlatch " : ".gate ") + master_name;
+        = ((cell->isSequential()) ? ".mlatch " : ".gate ") + master_name;
     std::string current_connections, current_clock;
     std::set<std::string> current_clocks;
 
@@ -250,10 +250,10 @@ bool Blif::writeBlif(const char* file_name, bool write_arrival_requireds)
 
     current_gate += current_connections;
 
-    if (cell->hasSequentials() && current_clocks.size() != 1) {
+    if (cell->isSequential() && current_clocks.size() != 1) {
       continue;
     }
-    if (cell->hasSequentials()) {
+    if (cell->isSequential()) {
       current_gate += " " + current_clock;
     }
 

src/cut/src/blif.cpp

@@ -212,7 +212,7 @@ void ConnectPinToDriver(
   abc::Abc_Obj_t* abc_net = abc::Abc_NtkCreateNet(&abc_network);
 
   if (network->isTopInstance(driver_instance)
-      || network->libertyCell(driver_instance)->hasSequentials()) {
+      || network->libertyCell(driver_instance)->isSequential()) {
     abc::Abc_Obj_t* abc_input = abc::Abc_NtkCreatePi(&abc_network);
     abc::Abc_ObjAddFanin(abc_net, abc_input);
     std::string driver_name = network->name(driver);

src/cut/src/logic_cut.cpp

@@ -5603,7 +5603,7 @@ bool dbNetwork::isValidFlop(odb::dbInst* FF) const
     return false;
   }
   const LibertyCell* lib_cell = testCell(cell);
-  if (lib_cell == nullptr || !lib_cell->hasSequentials()) {
+  if (lib_cell == nullptr || !lib_cell->isSequential()) {
     return false;
   }