Merge remote-tracking branch 'private/master' into dpl-dpo-load-macro-flipping

Author: gudeh

MODULE.bazel

@@ -250,7 +250,7 @@ alias(
     visibility = ["//visibility:public"],
 )
 """,
-    path = "bazel",
+    path = "bazel/slang-compat",
 )
 
 # --- Overrides ---

bazel/slang-compat/README

@@ -0,0 +1,3 @@
+Placeholder directory for the @slang alias build
+file to internally manifest.
+(see MODULE.bazel, new_local_repository(name="slang"))

src/OpenRoad.cc

@@ -520,6 +520,7 @@ void OpenRoad::read3Dbx(const std::string& filename)
 {
   odb::ThreeDBlox parser(logger_, db_, sta_);
   parser.readDbx(filename);
+  db_->constructUnfoldedModel();
   db_->triggerPostRead3Dbx(db_->getChip());
   check3DBlox();
 }

src/dbSta/test/cpp/TestReadVerilog.cpp

@@ -185,4 +185,74 @@ TEST_F(TestReadVerilog, DeepDescendantModBTermCollision)
   EXPECT_EQ(txclk_modnet->getModBTerms().size(), 1u);
 }
 
+TEST_F(TestReadVerilog, EscapedBracketScalarNames)
+{
+  const testing::TestInfo* test_info
+      = testing::UnitTest::GetInstance()->current_test_info();
+  const std::string test_name
+      = std::string(test_info->test_suite_name()) + "_" + test_info->name();
+
+  readVerilogAndSetup(test_name + ".v", /*init_default_sdc=*/false);
+
+  odb::dbBTerm* raw_bterm = block_->findBTerm("foo[3]");
+  odb::dbBTerm* leading_escape_bterm = block_->findBTerm("\\foo[3]");
+  odb::dbBTerm* escaped_bterm = block_->findBTerm("foo\\[3\\]");
+  EXPECT_EQ(raw_bterm, nullptr);
+  EXPECT_EQ(leading_escape_bterm, nullptr);
+  ASSERT_NE(escaped_bterm, nullptr);
+  EXPECT_STREQ(escaped_bterm->getConstName(), "foo\\[3\\]");
+
+  odb::dbModule* child = block_->findModule("child");
+  ASSERT_NE(child, nullptr);
+
+  EXPECT_EQ(child->findModBTerm("foo[3]"), nullptr);
+  EXPECT_EQ(child->findModBTerm("\\foo[3]"), nullptr);
+  odb::dbModBTerm* escaped_modbterm = child->findModBTerm("foo\\[3\\]");
+  ASSERT_NE(escaped_modbterm, nullptr);
+
+  EXPECT_EQ(child->getModNet("foo[3]"), nullptr);
+  EXPECT_EQ(child->getModNet("\\foo[3]"), nullptr);
+  odb::dbModNet* escaped_modnet = child->getModNet("foo\\[3\\]");
+  ASSERT_NE(escaped_modnet, nullptr);
+  EXPECT_EQ(escaped_modbterm->getModNet(), escaped_modnet);
+}
+
+TEST_F(TestReadVerilog, BusBitAndEscapedScalarAreDistinct)
+{
+  const testing::TestInfo* test_info
+      = testing::UnitTest::GetInstance()->current_test_info();
+  const std::string test_name
+      = std::string(test_info->test_suite_name()) + "_" + test_info->name();
+
+  readVerilogAndSetup(test_name + ".v", /*init_default_sdc=*/false);
+
+  odb::dbBTerm* bus_bit_bterm = block_->findBTerm("foo[3]");
+  odb::dbBTerm* leading_escape_bterm = block_->findBTerm("\\foo[3]");
+  odb::dbBTerm* escaped_bterm = block_->findBTerm("foo\\[3\\]");
+  ASSERT_NE(bus_bit_bterm, nullptr);
+  EXPECT_EQ(leading_escape_bterm, nullptr);
+  ASSERT_NE(escaped_bterm, nullptr);
+  EXPECT_NE(bus_bit_bterm, escaped_bterm);
+
+  odb::dbModule* child = block_->findModule("child");
+  ASSERT_NE(child, nullptr);
+
+  odb::dbModBTerm* bus_port = child->findModBTerm("foo");
+  odb::dbModBTerm* bus_bit_port = child->findModBTerm("foo[3]");
+  odb::dbModBTerm* escaped_port = child->findModBTerm("foo\\[3\\]");
+  ASSERT_NE(bus_port, nullptr);
+  ASSERT_NE(bus_bit_port, nullptr);
+  EXPECT_EQ(child->findModBTerm("\\foo[3]"), nullptr);
+  ASSERT_NE(escaped_port, nullptr);
+  EXPECT_NE(bus_bit_port, escaped_port);
+
+  odb::dbModNet* bus_bit_modnet = child->getModNet("foo[3]");
+  odb::dbModNet* escaped_modnet = child->getModNet("foo\\[3\\]");
+  ASSERT_NE(bus_bit_modnet, nullptr);
+  EXPECT_EQ(child->getModNet("\\foo[3]"), nullptr);
+  ASSERT_NE(escaped_modnet, nullptr);
+  EXPECT_NE(bus_bit_modnet, escaped_modnet);
+  EXPECT_EQ(escaped_port->getModNet(), escaped_modnet);
+}
+
 }  // namespace sta

src/dbSta/test/cpp/TestReadVerilog_BusBitAndEscapedScalarAreDistinct.v

@@ -0,0 +1,29 @@
+module top (foo,
+    \foo[3] ,
+    out_bus,
+    out_scalar);
+ input [7:0] foo;
+ input \foo[3] ;
+ output out_bus;
+ output out_scalar;
+
+ child u_child (.foo(foo),
+    .\foo[3] (\foo[3] ),
+    .out_bus(out_bus),
+    .out_scalar(out_scalar));
+endmodule
+
+module child (foo,
+    \foo[3] ,
+    out_bus,
+    out_scalar);
+ input [7:0] foo;
+ input \foo[3] ;
+ output out_bus;
+ output out_scalar;
+
+ BUF_X1 bus_load (.A(foo[3]),
+    .Z(out_bus));
+ BUF_X1 scalar_load (.A(\foo[3] ),
+    .Z(out_scalar));
+endmodule

src/dbSta/test/cpp/TestReadVerilog_EscapedBracketScalarNames.v

@@ -0,0 +1,17 @@
+module top (\foo[3] ,
+    out);
+ input \foo[3] ;
+ output out;
+
+ child u_child (.\foo[3] (\foo[3] ),
+    .out(out));
+endmodule
+
+module child (\foo[3] ,
+    out);
+ input \foo[3] ;
+ output out;
+
+ BUF_X1 load (.A(\foo[3] ),
+    .Z(out));
+endmodule

src/odb/src/db/dbDatabase.cpp

@@ -1212,7 +1212,6 @@ void dbDatabase::triggerPostRead3Dbx(dbChip* chip)
   for (dbDatabaseObserver* observer : db->observers_) {
     observer->postRead3Dbx(chip);
   }
-  constructUnfoldedModel();
 }
 
 void dbDatabase::triggerPostReadDb()

src/odb/src/db/dbInsertBuffer.cpp

@@ -24,6 +24,25 @@
 
 namespace odb {
 
+static std::string replaceBracketsWithUnderscores(std::string_view name)
+{
+  std::string sanitized_name;
+  sanitized_name.reserve(name.size());
+
+  for (size_t i = 0; i < name.size(); i++) {
+    const char ch = name[i];
+    if (ch == '\\' && i + 1 < name.size()
+        && (name[i + 1] == '[' || name[i + 1] == ']')) {
+      sanitized_name += '_';
+      i++;
+      continue;
+    }
+    sanitized_name += (ch == '[' || ch == ']') ? '_' : ch;
+  }
+
+  return sanitized_name;
+}
+
 dbInsertBuffer::dbInsertBuffer(dbNet* net)
     : net_(net),
       block_(net ? net->getBlock() : nullptr),
@@ -495,6 +514,12 @@ dbNet* dbInsertBuffer::createNewFlatNet(
     new_net_uniquify = dbNameUniquifyType::IF_NEEDED;
   }
 
+  if (bterm == nullptr) {
+    // New split nets are scalar wires. Keep their generated names easy to read
+    // by replacing bracket characters before ODB stores the name.
+    new_net_name = replaceBracketsWithUnderscores(new_net_name);
+  }
+
   // Create a new net
   dbNet* new_net = dbNet::create(
       block_, new_net_name.c_str(), new_net_uniquify, target_module_);
@@ -513,7 +538,10 @@ std::string dbInsertBuffer::makeUniqueHierName(const dbModule* module,
                                                const std::string& base_name,
                                                const char* suffix) const
 {
-  std::string name = (suffix == nullptr) ? base_name : base_name + suffix;
+  // insertBuffer only punches scalar hierarchy ports, never bus ports.
+  std::string scalar_base_name = replaceBracketsWithUnderscores(base_name);
+  std::string name
+      = (suffix == nullptr) ? scalar_base_name : scalar_base_name + suffix;
   std::string full = block_->makeNewNetName(
       module, name.c_str(), dbNameUniquifyType::IF_NEEDED_WITH_UNDERSCORE);
   return std::string(block_->getBaseName(full.c_str()));

src/pdn/src/straps.cpp

@@ -1590,6 +1590,19 @@ bool PadDirectConnectionStraps::refineShape(
 
 bool PadDirectConnectionStraps::isTargetShape(const Shape* shape) const
 {
+  // Pad direct connections run from a pad pin toward the core power grid.  They
+  // must not target shapes that belong to an instance (macro) grid: those
+  // stripes sit inside the core over the macro, and snapping a pad connection
+  // to them drags the connection deep into the core (issue #10490).  Only
+  // shapes owned by core/existing grids are valid landing targets.
+  const auto* component = shape->getGridComponent();
+  if (component != nullptr) {
+    const auto* grid = component->getGrid();
+    if (grid != nullptr && grid->type() == Grid::kInstance) {
+      return false;
+    }
+  }
+
   if (target_shapes_type_) {
     return shape->getType() == target_shapes_type_.value();
   }

src/pdn/test/BUILD

@@ -117,6 +117,7 @@ COMPULSORY_TESTS = [
     "pads_black_parrot_flipchip_connect_overpads",
     "pads_black_parrot_grid_define",
     "pads_black_parrot_limit_connect",
+    "pads_black_parrot_macro_grid",
     "pads_black_parrot_max_width",
     "pads_black_parrot_no_connect",
     "pads_black_parrot_offset",