add latch-based RAM

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

Author: tnguy19

src/ram/include/ram/ram.h

@@ -92,6 +92,7 @@ class RamGen
                 int num_words,
                 int column_mux_ratio,
                 int read_ports,
+                bool use_latch,
                 odb::dbMaster* storage_cell,
                 odb::dbMaster* tristate_cell,
                 odb::dbMaster* inv_cell,
@@ -197,6 +198,7 @@ class RamGen
   odb::dbMaster* clock_gate_cell_{nullptr};
   odb::dbMaster* buffer_cell_{nullptr};
   odb::dbMaster* aoi22_cell_{nullptr};
+  odb::dbMaster* latch_cell_{nullptr};
   odb::dbMaster* tapcell_{nullptr};
 
   std::map<PortRole, std::string> storage_ports_;
@@ -205,6 +207,7 @@ class RamGen
   std::map<PortRole, std::string> and2_ports_;
   std::map<PortRole, std::string> clock_gate_ports_;
   std::map<PortRole, std::string> buffer_ports_;
+  std::map<PortRole, std::string> latch_ports_;
 
   std::vector<odb::dbBTerm*> addr_inputs_;
   std::vector<odb::dbBTerm*> data_inputs_;
@@ -213,6 +216,7 @@ class RamGen
   std::string aoi22_in_a1_, aoi22_in_a2_, aoi22_in_b1_, aoi22_in_b2_,
       aoi22_out_;
   Grid ram_grid_;
+  bool use_latch_{false};
 };
 
 }  // namespace ram

src/ram/src/ram.cpp

@@ -120,13 +120,23 @@ std::unique_ptr<Cell> RamGen::makeBit(const std::string& prefix,
 
   auto storage_net = makeNet(prefix, "storage");
 
-  makeInst(bit_cell.get(),
-           prefix,
-           "bit",
-           storage_cell_,
-           {{storage_ports_[{PortRoleType::Clock, 0}], clock},
-            {storage_ports_[{PortRoleType::DataIn, 0}], data_input},
-            {storage_ports_[{PortRoleType::DataOut, 0}], storage_net}});
+  if (!use_latch_) {
+    makeInst(bit_cell.get(),
+             prefix,
+             "bit",
+             storage_cell_,
+             {{storage_ports_[{PortRoleType::Clock, 0}], clock},
+              {storage_ports_[{PortRoleType::DataIn, 0}], data_input},
+              {storage_ports_[{PortRoleType::DataOut, 0}], storage_net}});
+  } else {
+    makeInst(bit_cell.get(),
+             prefix,
+             "bit",
+             latch_cell_,
+             {{latch_ports_[{PortRoleType::Clock, 0}], clock},
+              {latch_ports_[{PortRoleType::DataIn, 0}], data_input},
+              {latch_ports_[{PortRoleType::DataOut, 0}], storage_net}});
+  }
 
   for (int read_port = 0; read_port < read_ports; ++read_port) {
     makeInst(
@@ -225,19 +235,6 @@ void RamGen::makeSlice(const int slice_idx,
               {and2_ports_[{PortRoleType::DataOut, 0}], write_sel}});
   }
 
-  // Write path: this net is row_select AND with word_select so clock gate only
-  // fires for the addressed word within the row. Read path handled by AOI mux.
-  // word_select is nullptr when column_mux_ratio=1 (no mux needed).
-  dbNet* write_sel = selects[0];
-  if (word_select) {
-    write_sel = makeNet(prefix, "write_sel");
-    makeInst(sel_cell.get(),
-             prefix,
-             "word_and",
-             and2_cell_,
-             {{"A", selects[0]}, {"B", word_select}, {"X", write_sel}});
-  }
-
   // Make clock and
   // this AND gate needs to be fed a net created by a decoder
   // adding any net will automatically connect with any port
@@ -627,31 +624,33 @@ void RamGen::findMasters()
   }
   and2_ports_ = buildPortMap(and2_cell_);
 
-  if (!storage_cell_) {
-    // FIXME
-    // Still needs changes to get right type of flip-flop
-    storage_cell_ = findMaster(
-        [](sta::LibertyPort* port) {
-          if (!port->isRegOutput()) {
-            return false;
-          }
-          // looking for DFF specifically
-          auto cell = port->libertyCell();
-          auto port_iter = cell->portIterator();
-          while (port_iter->hasNext()) {
-            auto p = port_iter->next()->libertyPort();
-            // check to filter out latches
-            if (p && p->isLatchData()) {
-              delete port_iter;
+  if (!use_latch_) {
+    if (!storage_cell_) {
+      // FIXME
+      // Still needs changes to get right type of flip-flop
+      storage_cell_ = findMaster(
+          [](sta::LibertyPort* port) {
+            if (!port->isRegOutput()) {
               return false;
             }
-          }
-          delete port_iter;
-          return true;
-        },
-        "storage");
+            // looking for DFF specifically
+            auto cell = port->libertyCell();
+            auto port_iter = cell->portIterator();
+            while (port_iter->hasNext()) {
+              auto p = port_iter->next()->libertyPort();
+              // check to filter out latches
+              if (p && p->isLatchData()) {
+                delete port_iter;
+                return false;
+              }
+            }
+            delete port_iter;
+            return true;
+          },
+          "storage");
+    }
+    storage_ports_ = buildPortMap(storage_cell_);
   }
-  storage_ports_ = buildPortMap(storage_cell_);
 
   if (!clock_gate_cell_) {
     clock_gate_cell_ = findMaster(
@@ -670,6 +669,39 @@ void RamGen::findMasters()
   }
   buffer_ports_ = buildPortMap(buffer_cell_);
 
+  // latch cells for latch-based ram: find neg/pos latch cell
+  if (use_latch_ && !latch_cell_) {
+    latch_cell_ = findMaster(
+        [](sta::LibertyPort* port) {
+          if (!port->direction()->isOutput()) {
+            return false;
+          }
+          auto cell = port->libertyCell();
+          if (!cell->hasSequentials()) {
+            return false;
+          }
+          bool has_latch_data = false;
+          bool has_gate = false;
+          auto port_iter = cell->portIterator();
+          while (port_iter->hasNext()) {
+            auto p = static_cast<sta::ConcretePort*>(port_iter->next());
+            auto lp = p->libertyPort();
+            if (lp && lp->isLatchData()) {
+              has_latch_data = true;
+            }
+            if (std::string(p->name()) == "GATE"
+                || std::string(p->name()) == "G") {
+              has_gate = true;
+            }
+          }
+          delete port_iter;
+          return has_latch_data && has_gate;
+        },
+        "latch");
+  }
+
+  latch_ports_ = buildPortMap(latch_cell_);
+
   // aoi cells used for column mux functionality when column_mux_ratio > 1
   // uses truth table simulation to identify AOI22 and discover port names
   // to work for all PDKs, avoiding hardcoding PDK-specific expression parsing
@@ -1021,6 +1053,7 @@ void RamGen::generate(const int mask_size,
                       const int num_words,
                       const int column_mux_ratio,
                       const int read_ports,
+                      const bool use_latch,
                       dbMaster* storage_cell,
                       dbMaster* tristate_cell,
                       dbMaster* inv_cell,
@@ -1078,6 +1111,7 @@ void RamGen::generate(const int mask_size,
 
   logger_->info(RAM, 3, "Generating {}", ram_name);
 
+  use_latch_ = use_latch;
   storage_cell_ = storage_cell;
   tristate_cell_ = tristate_cell;
   inv_cell_ = inv_cell;
@@ -1086,6 +1120,7 @@ void RamGen::generate(const int mask_size,
   clock_gate_cell_ = nullptr;
   buffer_cell_ = nullptr;
   aoi22_cell_ = nullptr;
+  latch_cell_ = nullptr;
   findMasters();
 
   auto chip = db_->getChip();
@@ -1181,19 +1216,6 @@ void RamGen::generate(const int mask_size,
       ram_grid_.addCell(std::move(decoder_and_cell), col_cell_count);
     }
   }
-} else {
-   word_decoder_nets[row] = selectNets(decoder_name, read_ports);
-  auto decoder_and_cell = makeDecoder(decoder_name,
-                                      num_rows,
-                                      read_ports,
-                                      word_decoder_nets[row],
-                                      decoder_input_nets[row]);
-  ram_grid_.addCell(std::move(decoder_and_cell), col_cell_count);
-}
-  }
-
-  std::unique_ptr<Cell> inv_sel_cell;
-  std::unique_ptr<Cell> word_sel_cell;
 
   std::unique_ptr<Cell> inv_sel_cell;
   std::unique_ptr<Cell> word_sel_cell;
@@ -1301,6 +1323,17 @@ void RamGen::generate(const int mask_size,
     }
   }
 
+  // For latch-based ram: mid_nets carry data from negative latch down to all
+  // pos latches per bit in the same column
+  vector<dbNet*> mid_nets(word_size);
+  dbNet* clk_b_net = nullptr;
+  if (use_latch_) {
+    clk_b_net = makeNet("global", "clk_b");
+    for (int bit = 0; bit < word_size; ++bit) {
+      mid_nets[bit] = makeNet("mid", fmt::format("b{}", bit));
+    }
+  }
+
   // For column_mux_ratio > 1, create one shared select_b net per row before
   // iterating over word_idx. All words in the same row share this net as the
   // tristate TE_B enable signal. Only word_idx=0 instantiates the select_inv
@@ -1337,7 +1370,7 @@ void RamGen::generate(const int mask_size,
                word_decoder_nets[row],
                shared_select_b_nets,
                (word_idx == 0 || column_mux_ratio == 1),
-               D_nets,
+               use_latch_ ? mid_nets : D_nets,
                word_output_nets);
     }
   }
@@ -1437,6 +1470,54 @@ void RamGen::generate(const int mask_size,
     }
   }
 
+  if (use_latch_) {
+    auto clk_inv_cell = std::make_unique<Cell>();
+    makeInst(clk_inv_cell.get(),
+             "neg_row",
+             "clk_inv",
+             inv_cell_,
+             {{inv_ports_[{PortRoleType::DataIn, 0}], clock->getNet()},
+              {inv_ports_[{PortRoleType::DataOut, 0}], clk_b_net}});
+    ram_grid_.addCell(std::move(clk_inv_cell), col_cell_count);
+
+    const int nl_col_offset = (column_mux_ratio == 4) ? 1 : 0;
+
+    for (int slice = 0; slice < slices_per_word; ++slice) {
+      for (int bit = 0; bit < mask_size; ++bit) {
+        const int global_bit = slice * mask_size + bit;
+        const int group_start
+            = slice * (mask_size * column_mux_ratio + column_mux_ratio)
+              + bit * column_mux_ratio;
+        const int nl_col = group_start + nl_col_offset;
+        for (int c = group_start; c < group_start + column_mux_ratio; ++c) {
+          if (c == nl_col) {
+            auto nl_cell = std::make_unique<Cell>();
+            makeInst(
+                nl_cell.get(),
+                fmt::format("neg_lat_b{}", global_bit),
+                "nlat",
+                latch_cell_,
+                {{latch_ports_[{PortRoleType::Clock, 0}], clk_b_net},
+                 {latch_ports_[{PortRoleType::DataIn, 0}], D_nets[global_bit]},
+                 {latch_ports_[{PortRoleType::DataOut, 0}],
+                  mid_nets[global_bit]}});
+            ram_grid_.addCell(std::move(nl_cell), c);
+          } else {
+            ram_grid_.addCell(nullptr, c);
+          }
+        }
+      }
+    }
+    for (int slice = 0; slice < slices_per_word; ++slice) {
+      for (int w = 0; w < column_mux_ratio; ++w) {
+        int sel_col = slice * (mask_size * column_mux_ratio + column_mux_ratio)
+                      + mask_size * column_mux_ratio + w;
+        ram_grid_.addCell(nullptr, sel_col);
+      }
+    }
+    ram_grid_.addCell(nullptr, col_cell_count);
+  }
+
   for (int slice = 0; slice < slices_per_word; ++slice) {
     for (int bit = 0; bit < mask_size; ++bit) {
       int bit_idx = bit + slice * mask_size;
@@ -1460,6 +1541,10 @@ void RamGen::generate(const int mask_size,
     ram_grid_.addCell(std::move(word_sel_cell), col_cell_count - 1);
   }
 
+  // One extra row at the top for placing input buffers, one extra row for
+  // negative latches if use latch-based ram
+  const int num_rows_grid = num_rows + 1 + (use_latch_ ? 1 : 0);
+
   auto cell_inv_layout = std::make_unique<Layout>(odb::vertical);
   // check for AND gate, specific case for 2 words
   int inv_col_cells = 0;
@@ -1500,8 +1585,8 @@ void RamGen::generate(const int mask_size,
       ++inv_col_cells;
     }
   }
-  // Pad remaining slots so this column matches the grid height (num_rows + 1)
-  while (inv_col_cells < num_rows + 1) {
+  // Pad remaining slots so this column matches the grid height (num_rows_grid)
+  while (inv_col_cells < num_rows_grid) {
     cell_inv_layout->addCell(nullptr);
     ++inv_col_cells;
   }
@@ -1515,7 +1600,7 @@ void RamGen::generate(const int mask_size,
   if (tapcell_) {
     // max tap distance specified is greater than the length of ram
     if (ram_grid_.getRowWidth() <= max_tap_dist) {
-      auto tapcell_layout = generateTapColumn(num_rows, 0);
+      auto tapcell_layout = generateTapColumn(num_rows_grid - 1, 0);
       ram_grid_.insertLayout(std::move(tapcell_layout), 0);
     } else {
       // needed this calculation so first cells have right distance
@@ -1526,7 +1611,8 @@ void RamGen::generate(const int mask_size,
       for (int col = 0; col < ram_grid_.numLayouts(); ++col) {
         if (nearest_tap + ram_grid_.getLayoutWidth(col) >= max_tap_dist) {
           // if the nearest_tap is too far, generate tap column
-          auto tapcell_layout = generateTapColumn(num_rows, tapcell_count);
+          auto tapcell_layout
+              = generateTapColumn(num_rows_grid - 1, tapcell_count);
           ram_grid_.insertLayout(std::move(tapcell_layout), col);
           ++col;  // col adjustment after insertion
           nearest_tap = 0;
@@ -1536,7 +1622,8 @@ void RamGen::generate(const int mask_size,
       }
       // check for last column in the grid
       if (nearest_tap >= max_tap_dist) {
-        auto tapcell_layout = generateTapColumn(num_rows, tapcell_count);
+        auto tapcell_layout
+            = generateTapColumn(num_rows_grid - 1, tapcell_count);
         ram_grid_.addLayout(std::move(tapcell_layout));
       }
     }
@@ -1550,8 +1637,6 @@ void RamGen::generate(const int mask_size,
 
   int num_sites = ram_grid_.getRowWidth() / db_sites->getWidth();
 
-  // One extra row at the top for placing input buffers
-  const int num_rows_grid = num_rows + 1;
   for (int i = 0; i < num_rows_grid; ++i) {
     auto row_name = fmt::format("RAM_ROW{}", i);
     auto y_coord = i * ram_grid_.getHeight();