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eder-matheuseder-matheus
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Merge pull request #10832 from tnguy19/ram-remove-power-ground-pin-args
ram: remove explicit power_pin/ground_pin args from 2r1w test tcl files
2 parents 58fe30b + 8ae3311 commit 6e7eaab

7 files changed

Lines changed: 68 additions & 63 deletions

‎src/ram/test/BUILD‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,10 @@ package(features = ["layering_check"])
66

77
# From CMakeLists.txt or_integration_tests(TESTS
88
COMPULSORY_TESTS = [
9-
"make_8x8_sky130",
9+
"make_7x7_2r1w_nangate45",
1010
"make_7x7_nangate45",
11+
"make_8x8_2r1w_sky130",
12+
"make_8x8_sky130",
1113
]
1214

1315
PASSFAIL_TESTS = [
@@ -49,12 +51,19 @@ filegroup(
4951
test_name + ".*",
5052
],
5153
) + {
54+
"make_7x7_2r1w_nangate45": [
55+
"make_7x7_2r1w_nangate45_behavioral.vok",
56+
"Nangate45/Nangate45.lef",
57+
"Nangate45/Nangate45_tech.lef",
58+
"Nangate45/Nangate45_typ.lib",
59+
],
5260
"make_7x7_nangate45": [
5361
"make_7x7_nangate45_behavioral.vok",
5462
"Nangate45/Nangate45.lef",
5563
"Nangate45/Nangate45_tech.lef",
5664
"Nangate45/Nangate45_typ.lib",
5765
],
66+
"make_8x8_2r1w_sky130": ["make_8x8_2r1w_sky130_behavioral.vok"],
5867
"make_8x8_sky130": ["make_8x8_sky130_behavioral.vok"],
5968
}.get(test_name, []),
6069
)

‎src/ram/test/make_7x7_2r1w_nangate45.lefok‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -265,6 +265,34 @@ MACRO RAM7x7
265265
RECT 43.705 11.06 43.845 11.2 ;
266266
END
267267
END Q1[6]
268+
PIN VDD
269+
DIRECTION INOUT ;
270+
USE POWER ;
271+
PORT
272+
LAYER metal4 ;
273+
RECT 49.43 11.06 49.57 11.2 ;
274+
RECT 49.43 0 49.57 0.14 ;
275+
RECT 40.43 11.06 40.57 11.2 ;
276+
RECT 40.43 0 40.57 0.14 ;
277+
RECT 31.43 11.06 31.57 11.2 ;
278+
RECT 31.43 0 31.57 0.14 ;
279+
RECT 22.43 11.06 22.57 11.2 ;
280+
RECT 22.43 0 22.57 0.14 ;
281+
RECT 13.43 11.06 13.57 11.2 ;
282+
RECT 13.43 0 13.57 0.14 ;
283+
RECT 4.43 11.06 4.57 11.2 ;
284+
RECT 4.43 0 4.57 0.14 ;
285+
LAYER metal1 ;
286+
RECT 56.55 9.76 56.62 9.84 ;
287+
RECT 0 9.76 0.07 9.84 ;
288+
RECT 56.55 6.96 56.62 7.04 ;
289+
RECT 0 6.96 0.07 7.04 ;
290+
RECT 56.55 4.16 56.62 4.24 ;
291+
RECT 0 4.16 0.07 4.24 ;
292+
RECT 56.55 1.36 56.62 1.44 ;
293+
RECT 0 1.36 0.07 1.44 ;
294+
END
295+
END VDD
268296
PIN VSS
269297
DIRECTION INOUT ;
270298
USE GROUND ;
@@ -295,34 +323,6 @@ MACRO RAM7x7
295323
RECT 0 -0.04 0.07 0.04 ;
296324
END
297325
END VSS
298-
PIN VDD
299-
DIRECTION INOUT ;
300-
USE POWER ;
301-
PORT
302-
LAYER metal4 ;
303-
RECT 49.43 11.06 49.57 11.2 ;
304-
RECT 49.43 0 49.57 0.14 ;
305-
RECT 40.43 11.06 40.57 11.2 ;
306-
RECT 40.43 0 40.57 0.14 ;
307-
RECT 31.43 11.06 31.57 11.2 ;
308-
RECT 31.43 0 31.57 0.14 ;
309-
RECT 22.43 11.06 22.57 11.2 ;
310-
RECT 22.43 0 22.57 0.14 ;
311-
RECT 13.43 11.06 13.57 11.2 ;
312-
RECT 13.43 0 13.57 0.14 ;
313-
RECT 4.43 11.06 4.57 11.2 ;
314-
RECT 4.43 0 4.57 0.14 ;
315-
LAYER metal1 ;
316-
RECT 56.55 9.76 56.62 9.84 ;
317-
RECT 0 9.76 0.07 9.84 ;
318-
RECT 56.55 6.96 56.62 7.04 ;
319-
RECT 0 6.96 0.07 7.04 ;
320-
RECT 56.55 4.16 56.62 4.24 ;
321-
RECT 0 4.16 0.07 4.24 ;
322-
RECT 56.55 1.36 56.62 1.44 ;
323-
RECT 0 1.36 0.07 1.44 ;
324-
END
325-
END VDD
326326
OBS
327327
LAYER metal1 ;
328328
RECT 0 -0.07 56.62 11.27 ;

‎src/ram/test/make_7x7_2r1w_nangate45.ok‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -115,4 +115,4 @@
115115
[INFO DRT-0179] Init gr pin query.
116116
No differences found.
117117
No differences found.
118-
No differences found.
118+
No differences found.

‎src/ram/test/make_7x7_2r1w_nangate45.tcl‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,6 @@ generate_ram \
1616
-r_ports 2 \
1717
-w_ports 1 \
1818
-storage_cell DFF_X1 \
19-
-power_pin VDD \
20-
-ground_pin VSS \
2119
-routing_layer {metal1 0.08} \
2220
-ver_layer {metal4 0.14 9} \
2321
-hor_layer {metal3 0.08 8} \

‎src/ram/test/make_8x8_2r1w_sky130.lefok‎

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -289,33 +289,6 @@ MACRO RAM8x8
289289
RECT 120.68 23.995 120.82 24.48 ;
290290
END
291291
END Q1[7]
292-
PIN VSS
293-
DIRECTION INOUT ;
294-
USE GROUND ;
295-
PORT
296-
LAYER met3 ;
297-
RECT 154.72 19.76 155.02 20.24 ;
298-
RECT 0 19.76 0.3 20.24 ;
299-
LAYER met2 ;
300-
RECT 119.76 24.34 120.24 24.48 ;
301-
RECT 119.76 0 120.24 0.14 ;
302-
RECT 79.76 24.34 80.24 24.48 ;
303-
RECT 79.76 0 80.24 0.14 ;
304-
RECT 39.76 24.34 40.24 24.48 ;
305-
RECT 39.76 0 40.24 0.14 ;
306-
LAYER met1 ;
307-
RECT 154.88 21.52 155.02 22 ;
308-
RECT 0 21.52 0.14 22 ;
309-
RECT 154.88 16.08 155.02 16.56 ;
310-
RECT 0 16.08 0.14 16.56 ;
311-
RECT 154.88 10.64 155.02 11.12 ;
312-
RECT 0 10.64 0.14 11.12 ;
313-
RECT 154.88 5.2 155.02 5.68 ;
314-
RECT 0 5.2 0.14 5.68 ;
315-
RECT 154.88 -0.24 155.02 0.24 ;
316-
RECT 0 -0.24 0.14 0.24 ;
317-
END
318-
END VSS
319292
PIN VDD
320293
DIRECTION INOUT ;
321294
USE POWER ;
@@ -345,6 +318,33 @@ MACRO RAM8x8
345318
RECT 0 2.48 0.14 2.96 ;
346319
END
347320
END VDD
321+
PIN VSS
322+
DIRECTION INOUT ;
323+
USE GROUND ;
324+
PORT
325+
LAYER met3 ;
326+
RECT 154.72 19.76 155.02 20.24 ;
327+
RECT 0 19.76 0.3 20.24 ;
328+
LAYER met2 ;
329+
RECT 119.76 24.34 120.24 24.48 ;
330+
RECT 119.76 0 120.24 0.14 ;
331+
RECT 79.76 24.34 80.24 24.48 ;
332+
RECT 79.76 0 80.24 0.14 ;
333+
RECT 39.76 24.34 40.24 24.48 ;
334+
RECT 39.76 0 40.24 0.14 ;
335+
LAYER met1 ;
336+
RECT 154.88 21.52 155.02 22 ;
337+
RECT 0 21.52 0.14 22 ;
338+
RECT 154.88 16.08 155.02 16.56 ;
339+
RECT 0 16.08 0.14 16.56 ;
340+
RECT 154.88 10.64 155.02 11.12 ;
341+
RECT 0 10.64 0.14 11.12 ;
342+
RECT 154.88 5.2 155.02 5.68 ;
343+
RECT 0 5.2 0.14 5.68 ;
344+
RECT 154.88 -0.24 155.02 0.24 ;
345+
RECT 0 -0.24 0.14 0.24 ;
346+
END
347+
END VSS
348348
OBS
349349
LAYER li1 ;
350350
RECT 0 -0.24 155.02 24.72 ;

‎src/ram/test/make_8x8_2r1w_sky130.ok‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
[INFO RAM-0024] Behavioral Verilog written for RAM8x8
1111
[INFO PDN-0001] Inserting grid: ram_grid
1212
[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q0[0] Q1[0] ... ] to region 0.00u-155.02u at the TOP edge.
13-
[INFO PPL-0067] Restrict pins [ addr_w[0][0] addr_w[0][1] addr_w[0][2] addr_r[0][0] addr_r[0][1] ... ] to region 0.00u-24.48u at the RIGHT edge.
13+
[INFO PPL-0067] Restrict pins [ addr_w[0] addr_w[1] addr_w[2] addr_r0[0] addr_r0[1] ... ] to region 0.00u-24.48u at the RIGHT edge.
1414
[INFO PPL-0001] Number of available slots 364
1515
[INFO PPL-0002] Number of I/O 35
1616
[INFO PPL-0003] Number of I/O w/sink 35

‎src/ram/test/make_8x8_2r1w_sky130.tcl‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ read_liberty sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
77
read_lef sky130hd/sky130hd.tlef
88
read_lef sky130hd/sky130_fd_sc_hd_merged.lef
99

10-
set behavioral_file [make_result_file make_8x8_1rw1r_behavioral.v]
10+
set behavioral_file [make_result_file make_8x8_2rw1r_behavioral.v]
1111

1212
generate_ram \
1313
-mask_size 8 \
@@ -16,8 +16,6 @@ generate_ram \
1616
-r_ports 2 \
1717
-w_ports 1 \
1818
-storage_cell sky130_fd_sc_hd__dfxtp_1 \
19-
-power_pin VPWR \
20-
-ground_pin VGND \
2119
-routing_layer {met1 0.48} \
2220
-ver_layer {met2 0.48 40} \
2321
-hor_layer {met3 0.48 20} \

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