changes to accomodate for new changes in OpenSTA 6/30 pulling latest

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

Author: dsengupta0628

src/Design.cc

@@ -190,7 +190,7 @@ bool Design::isSequential(odb::dbMaster* master)
   if (!lib_cell) {
     return false;
   }
-  return lib_cell->hasSequentials();
+  return lib_cell->isSequential();
 }
 
 bool Design::isInClock(odb::dbInst* inst)

src/cts/src/LatencyBalancer.cpp

@@ -582,7 +582,7 @@ bool LatencyBalancer::propagateClock(odb::dbITerm* input)
     return true;
   }
   // Combinational components
-  if (!libertyCell->hasSequentials()) {
+  if (!libertyCell->isSequential()) {
     return true;
   }
   sta::LibertyPort* inputPort

src/cut/src/abc_library_factory.cpp

@@ -78,7 +78,7 @@ static bool IsCombinational(sta::LibertyCell* cell)
     return false;
   }
   return (!cell->isClockGate() && !cell->isPad() && !cell->isMacro()
-          && !cell->hasSequentials() && !cell->isLevelShifter()
+          && !cell->isSequential() && !cell->isLevelShifter()
           && !cell->isIsolationCell() && !cell->isMemory());
 }
 

src/cut/src/blif.cpp

@@ -95,7 +95,7 @@ bool Blif::writeBlif(const char* file_name, bool write_arrival_requireds)
     auto master_name = master->getName();
 
     std::string current_gate
-        = ((cell->hasSequentials()) ? ".mlatch " : ".gate ") + master_name;
+        = ((cell->isSequential()) ? ".mlatch " : ".gate ") + master_name;
     std::string current_connections, current_clock;
     std::set<std::string> current_clocks;
 
@@ -250,10 +250,10 @@ bool Blif::writeBlif(const char* file_name, bool write_arrival_requireds)
 
     current_gate += current_connections;
 
-    if (cell->hasSequentials() && current_clocks.size() != 1) {
+    if (cell->isSequential() && current_clocks.size() != 1) {
       continue;
     }
-    if (cell->hasSequentials()) {
+    if (cell->isSequential()) {
       current_gate += " " + current_clock;
     }
 

src/cut/src/logic_cut.cpp

@@ -212,7 +212,7 @@ void ConnectPinToDriver(
   abc::Abc_Obj_t* abc_net = abc::Abc_NtkCreateNet(&abc_network);
 
   if (network->isTopInstance(driver_instance)
-      || network->libertyCell(driver_instance)->hasSequentials()) {
+      || network->libertyCell(driver_instance)->isSequential()) {
     abc::Abc_Obj_t* abc_input = abc::Abc_NtkCreatePi(&abc_network);
     abc::Abc_ObjAddFanin(abc_net, abc_input);
     std::string driver_name = network->name(driver);

src/dbSta/src/dbNetwork.cc

@@ -5603,7 +5603,7 @@ bool dbNetwork::isValidFlop(odb::dbInst* FF) const
     return false;
   }
   const LibertyCell* lib_cell = testCell(cell);
-  if (lib_cell == nullptr || !lib_cell->hasSequentials()) {
+  if (lib_cell == nullptr || !lib_cell->isSequential()) {
     return false;
   }
 

src/dbSta/src/dbSta.cc

@@ -614,7 +614,7 @@ dbSta::InstType dbSta::getInstanceType(odb::dbInst* inst)
   if (lib_cell->isLevelShifter()) {
     return STD_LEVEL_SHIFT;
   }
-  if (lib_cell->hasSequentials()) {
+  if (lib_cell->isSequential()) {
     return STD_SEQUENTIAL;
   }
   if (lib_cell->portCount() == 0) {

src/dft/src/cells/ScanCellFactory.cpp

@@ -66,7 +66,7 @@ TypeOfCell IdentifyCell(odb::dbInst* inst, sta::dbSta* sta)
   sta::dbNetwork* db_network = sta->getDbNetwork();
   sta::LibertyCell* liberty_cell
       = GetLibertyCell(inst->getMaster(), db_network);
-  if (liberty_cell != nullptr && liberty_cell->hasSequentials()
+  if (liberty_cell != nullptr && liberty_cell->isSequential()
       && !inst->getMaster()->isBlock()) {
     // we assume that we are only dealing with one bit cells, but in the future
     // we could deal with multibit cells too

src/dft/src/replace/ScanReplace.cpp

@@ -278,7 +278,7 @@ void ScanReplace::collectScanCellAvailable()
       }
 
       // We only care about sequential cells in DFT
-      if (!liberty_cell->hasSequentials()) {
+      if (!liberty_cell->isSequential()) {
         continue;
       }
 
@@ -389,7 +389,7 @@ void ScanReplace::scanReplace(odb::dbBlock* block)
       continue;
     }
 
-    if (!from_liberty_cell->hasSequentials()
+    if (!from_liberty_cell->isSequential()
         || from_liberty_cell->isClockGate()) {
       // If the cell is not sequential, then there is nothing to replace
       continue;

src/dft/src/utils/Utils.cpp

@@ -54,7 +54,7 @@ bool IsSequentialCell(sta::dbNetwork* db_network, odb::dbInst* instance)
   odb::dbMaster* master = instance->getMaster();
   sta::Cell* master_cell = db_network->dbToSta(master);
   sta::LibertyCell* liberty_cell = db_network->libertyCell(master_cell);
-  return liberty_cell->hasSequentials();
+  return liberty_cell->isSequential();
 }
 
 odb::dbInst* ReplaceCell(