Merge pull request #10307 from oharboe/split-drop-eqy

test/orfs: drop eqy formal-equivalence scaffolding

Author: maliberty

test/orfs/eqy-flow.bzl

@@ -1,7 +1,6 @@
 load("@bazel-orfs//:sweep.bzl", "orfs_sweep")
 load("@rules_shell//shell:sh_test.bzl", "sh_test")
 load("//test/orfs:check_same.bzl", "check_same")
-load("//test/orfs:eqy-flow.bzl", "eqy_flow_test")
 
 package(features = ["layering_check"])
 
@@ -36,14 +35,6 @@ orfs_sweep(
     verilog_files = ["gcd.v"],
 )
 
-eqy_flow_test(
-    name = "gcd_eqy",
-    flow = "gcd",
-    module_top = "gcd",
-    tags = ["manual"],
-    verilog_files = ["gcd.v"],
-)
-
 filegroup(
     name = "gcd_floorplan_odb",
     srcs = [":gcd_floorplan"],

test/orfs/gcd/BUILD

@@ -78,23 +78,6 @@ CONFIGS = {name: config(name, rows, cols) for name, rows, cols in [
     config = config,
 ) for name, config in CONFIGS.items()]
 
-test_suite(
-    name = "eqy_tests",
-    tags = ["manual"],
-    tests = ["Element_eqy_{variant}".format(variant = name) for name in CONFIGS] +
-            [
-                "MockArray_eqy_{name}_{variant}".format(
-                    name = name,
-                    variant = variant,
-                )
-                for name in CONFIGS
-                for variant in [
-                    "flat",
-                    "base",
-                ]
-            ],
-)
-
 orfs_run(
     name = "write_macro_placement",
     src = ":MockArray_4x4_base_floorplan",

test/orfs/mock-array/BUILD

@@ -7,7 +7,6 @@ load("@rules_cc//cc:defs.bzl", "cc_binary")
 load("@rules_shell//shell:sh_test.bzl", "sh_test")
 load("@rules_verilator//verilator:defs.bzl", "verilator_cc_library")
 load("@rules_verilator//verilog:defs.bzl", "verilog_library")
-load("//test/orfs:eqy-flow.bzl", "eqy_flow_test")
 
 def verilog(name, **_kwargs):
     """Provide mock array verilog sources
@@ -148,13 +147,6 @@ def element(name, config):
         verilog_files = [":{name}_verilog".format(name = name)],
         variant = "{name}_base".format(name = name),
     )
-    eqy_flow_test(
-        name = "Element_eqy_{variant}".format(variant = name),
-        flow = "Element_{variant}_base".format(variant = name),
-        verilog_files = [":{name}_verilog".format(name = name)],
-        tags = ["manual"],
-        module_top = "Element",
-    )
 
 POWER_STAGES = {
     "cts": {
@@ -393,14 +385,6 @@ def mock_array(name, config):
             variant = variant,
             verilog_files = [":{name}_verilog".format(name = name)],
         )
-        eqy_flow_test(
-            name = "MockArray_eqy_{variant}".format(variant = variant),
-            flow = "MockArray_{variant}".format(variant = variant),
-            verilog_files = [":{name}_verilog".format(name = name)],
-            other_verilog_files = [":Element_eqy_{name}_final_verilog".format(name = name)],
-            tags = ["manual"],
-            module_top = "MockArray",
-        )
 
         for stage in POWER_STAGES:
             for macro in MACROS: