Merge pull request #10544 from eder-matheus/est_fix_vias

est: fix parasitic nodes for vias

Author: eder-matheus

src/dbSta/test/escape_slash.spefok

@@ -1017,31 +1017,49 @@ void EstimateParasitics::insertViaResistances(odb::dbTechLayer* pin_layer,
       if (cut_layer->getType() != odb::dbTechLayerType::CUT) {
         continue;
       }
-      sta::ParasiticNode* mid_node = parasitics->ensureParasiticNode(
-          parasitic, net, ++max_node_index, network_);
-
       const double cut_res
           = std::max(layer_res_[layer_idx][corner->index()], 1.0e-3);
 
+      // Resolve from/to endpoints first, so we only allocate a new mid_node
+      // when this iteration actually needs one. On the terminal iteration the
+      // resistor connects directly to the pin or tree anchor; if we had
+      // pre-allocated a mid_node here it would never be wired up and would
+      // become a floating ParasiticNode (singular row in the conductance
+      // matrix for Prima/CCS).
       sta::ParasiticNode* from_node = prev_node;
-      sta::ParasiticNode* to_node = mid_node;
+      sta::ParasiticNode* to_node = nullptr;
+      bool need_new_mid = true;
       if (pin_is_below) {
         if (layer_idx - 1 == pin_layer_idx) {
           from_node = pin_node;
-        } else if (layer_idx + 1 == tree_layer_idx) {
+        }
+        if (layer_idx + 1 == tree_layer_idx) {
           to_node = node;
+          need_new_mid = false;
         }
       } else {
         if (layer_idx - 1 == tree_layer_idx) {
           from_node = node;
-        } else if (layer_idx + 1 == pin_layer_idx) {
+        }
+        if (layer_idx + 1 == pin_layer_idx) {
           to_node = pin_node;
+          need_new_mid = false;
         }
       }
 
+      sta::ParasiticNode* mid_node = nullptr;
+      if (need_new_mid) {
+        mid_node = parasitics->ensureParasiticNode(
+            parasitic, net, ++max_node_index, network_);
+        to_node = mid_node;
+      }
+
       parasitics->makeResistor(
           parasitic, resistor_id++, cut_res, from_node, to_node);
 
+      // On the terminal iteration mid_node is nullptr and prev_node is unused
+      // by the next iteration (there is none); on every other iteration we
+      // chain through the freshly allocated mid_node.
       prev_node = mid_node;
     }
   }

src/dbSta/test/escape_slash_hier.spefok

@@ -3,9 +3,13 @@
 
 #include "MakeWireParasitics.h"
 
+#include <algorithm>
 #include <cmath>
 #include <cstddef>
+#include <iterator>
+#include <map>
 #include <string>
+#include <utility>
 #include <vector>
 
 #include "db_sta/SpefWriter.hh"
@@ -242,6 +246,67 @@ void MakeWireParasitics::makeRouteParasitics(sta::Parasitics* parasitics,
     parasitics->makeResistor(parasitic, resistor_id_++, res, n1, n2);
     parasitics->incrCap(n2, cap / 2.0);
   }
+
+  // Workaround: implicit-via post-pass.
+  //
+  // GRT does not always emit an explicit isVia=true segment at every
+  // layer transition along a route; coincident endpoints on adjacent
+  // routing levels are treated as implicitly connected. EST has historically
+  // taken GRoute literally, so any layer transition without an explicit via
+  // segment ends up as two distinct ParasiticNodes at the same (x, y) with
+  // no resistor between them -- a disconnected island in the parasitic
+  // network. That goes unnoticed by pi-Elmore-based delay calculators but
+  // produces a singular conductance matrix in Prima/CCS.
+  //
+  // Close the contract gap here: scan node_map for coincident endpoints on
+  // adjacent routing levels and, when no resistor already bridges them,
+  // insert one with the appropriate cut-layer resistance.
+  std::vector<std::pair<sta::ParasiticNode*, sta::ParasiticNode*>>
+      connected_pairs;
+  for (sta::ParasiticResistor* r : parasitics->resistors(parasitic)) {
+    sta::ParasiticNode* a = parasitics->node1(r);
+    sta::ParasiticNode* b = parasitics->node2(r);
+    connected_pairs.emplace_back(std::minmax(a, b));
+  }
+  std::ranges::sort(connected_pairs);
+
+  if (!node_map.empty()) {
+    auto prev_it = node_map.begin();
+    for (auto it = std::next(prev_it); it != node_map.end();
+         prev_it = it, ++it) {
+      const auto& prev_pt = prev_it->first;
+      const auto& curr_pt = it->first;
+      if (prev_pt.x() != curr_pt.x() || prev_pt.y() != curr_pt.y()) {
+        continue;
+      }
+      if (curr_pt.layer() != prev_pt.layer() + 1) {
+        // Not adjacent routing levels -- skipping signals that an
+        // intermediate routing-level node is missing entirely, which is a
+        // different bug worth surfacing rather than silently bridging.
+        continue;
+      }
+      sta::ParasiticNode* lo_node = prev_it->second;
+      sta::ParasiticNode* hi_node = it->second;
+      const std::pair<sta::ParasiticNode*, sta::ParasiticNode*> pair
+          = std::minmax(lo_node, hi_node);
+      auto bound_it = std::ranges::lower_bound(connected_pairs, pair);
+      if (bound_it != connected_pairs.end() && *bound_it == pair) {
+        continue;
+      }
+      odb::dbTechLayer* lower_routing
+          = tech_->findRoutingLayer(prev_pt.layer());
+      odb::dbTechLayer* cut_layer
+          = lower_routing ? lower_routing->getUpperLayer() : nullptr;
+      if (cut_layer == nullptr) {
+        // Top of stack or unresolved -- do not silently invent a resistor.
+        continue;
+      }
+      const float via_R = getCutLayerRes(cut_layer, corner);
+      parasitics->makeResistor(
+          parasitic, resistor_id_++, via_R, lo_node, hi_node);
+      connected_pairs.insert(bound_it, pair);
+    }
+  }
 }
 
 void MakeWireParasitics::makeParasiticsToPins(