test: Reduce escape slash regression

Replace the oversized escape_slash and escape_slash_hier regressions with minimal DEF-backed fixtures that preserve the targeted slash escaping cases.

The old tests depended on floorplan, placement, and CTS behavior even though they only validated Verilog and SPEF name escaping. The new fixtures keep one flat escaped slash path and one hierarchical escaped slash path while avoiding unrelated flow commands.

Update the expected Verilog, SPEF, and log goldens for the reduced designs.

Tested: RESULTS_DIR=/workspace/exp/escape_slash_min/final_flat openroad -no_init -no_splash -exit -metrics /workspace/exp/escape_slash_min/final_escape_slash.metrics.json escape_slash.tcl

Tested: RESULTS_DIR=/workspace/exp/escape_slash_min/final_hier openroad -no_init -no_splash -exit -metrics /workspace/exp/escape_slash_min/final_escape_slash_hier.metrics.json escape_slash_hier.tcl

Tested: git diff --check

Co-authored-by: OmX <omx@oh-my-codex.dev>

Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

Author: jhkim-pii

src/dbSta/test/escape_slash.def

@@ -0,0 +1,32 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN multi_sink ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 40000 11200 ) ;
+ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 105 BY 1 STEP 380 0 ;
+ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 105 BY 1 STEP 380 0 ;
+ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 105 BY 1 STEP 380 0 ;
+ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 105 BY 1 STEP 380 0 ;
+TRACKS X 190 DO 105 STEP 380 LAYER metal1 ;
+TRACKS Y 140 DO 40 STEP 280 LAYER metal1 ;
+TRACKS X 190 DO 105 STEP 380 LAYER metal2 ;
+TRACKS Y 140 DO 40 STEP 280 LAYER metal2 ;
+TRACKS X 190 DO 105 STEP 380 LAYER metal3 ;
+TRACKS Y 140 DO 40 STEP 280 LAYER metal3 ;
+COMPONENTS 3 ;
+    - hi_inst\/gclk2_inst CLKGATE_X1 + PLACED ( 760 2800 ) FS ;
+    - h1\/ff1 DFF_X1 + PLACED ( 6460 2800 ) FS ;
+    - ff0\/name DFF_X1 + PLACED ( 13680 2800 ) FS ;
+END COMPONENTS
+PINS 1 ;
+    - clk + NET clk + DIRECTION INPUT + USE SIGNAL
+      + PORT
+        + LAYER metal2 ( -70 -70 ) ( 70 70 )
+        + PLACED ( 190 2940 ) N ;
+END PINS
+NETS 2 ;
+    - clk ( PIN clk ) ( hi_inst\/gclk2_inst CK ) + USE SIGNAL ;
+    - hi_gclk2 ( hi_inst\/gclk2_inst GCK ) ( h1\/ff1 CK ) ( ff0\/name CK ) + USE SIGNAL ;
+END NETS
+END DESIGN