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Merge pull request #10291 from The-OpenROAD-Project-staging/cts_fix_exiting_tree_identification
cts: fix existing clock tree identification
2 parents dea422b + d549623 commit acbccf1

8 files changed

Lines changed: 701 additions & 4 deletions

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‎src/cts/src/TritonCTS.cpp‎

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1456,11 +1456,16 @@ bool TritonCTS::separateMacroRegSinks(
14561456
std::vector<std::pair<odb::dbInst*, odb::dbMTerm*>>& registerSinks,
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std::vector<std::pair<odb::dbInst*, odb::dbMTerm*>>& macroSinks)
14581458
{
1459+
odb::dbInst* skippedTimingBuf = nullptr;
1460+
14591461
for (odb::dbITerm* iterm : net->getITerms()) {
14601462
odb::dbInst* inst = iterm->getInst();
14611463

1462-
if (buffer_masters.find(inst->getMaster()) != buffer_masters.end()
1463-
&& inst->getSourceType() == odb::dbSourceType::TIMING) {
1464+
const bool isTimingBuffer
1465+
= buffer_masters.find(inst->getMaster()) != buffer_masters.end()
1466+
&& inst->getSourceType() == odb::dbSourceType::TIMING;
1467+
1468+
if (iterm->isOutputSignal() && isTimingBuffer) {
14641469
logger_->warn(CTS,
14651470
105,
14661471
"Net \"{}\" already has clock buffer {}. Skipping...",
@@ -1469,6 +1474,12 @@ bool TritonCTS::separateMacroRegSinks(
14691474
return false;
14701475
}
14711476

1477+
// TIMING buffer sinks are traversed via initOneClockTree, not as sinks.
1478+
if (iterm->isInputSignal() && isTimingBuffer) {
1479+
skippedTimingBuf = inst;
1480+
continue;
1481+
}
1482+
14721483
if (iterm->isInputSignal() && inst->isPlaced()) {
14731484
// Cells with insertion delay, macros, clock gaters and inverters that
14741485
// drive macros are put in the macro sinks.
@@ -1490,6 +1501,14 @@ bool TritonCTS::separateMacroRegSinks(
14901501
}
14911502
}
14921503
}
1504+
if (skippedTimingBuf && (registerSinks.size() + macroSinks.size()) < 2) {
1505+
logger_->warn(CTS,
1506+
110,
1507+
"Net \"{}\" already has clock buffer {}. Skipping...",
1508+
clockNet.getName(),
1509+
skippedTimingBuf->getName());
1510+
return false;
1511+
}
14931512

14941513
return true;
14951514
}

‎src/cts/test/BUILD‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ COMPULSORY_TESTS = [
1414
"array_max_wl",
1515
"array_no_blockages",
1616
"array_repair_clock_nets",
17+
"buffer_ports",
1718
"check_buffers",
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"check_buffers_blockages",
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"check_buffers_blockages_merge",

‎src/cts/test/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ or_integration_tests(
99
array_max_wl
1010
array_no_blockages
1111
array_repair_clock_nets
12+
buffer_ports
1213
check_buffers
1314
check_buffers_blockages
1415
colocated_sinks

‎src/cts/test/buffer_ports.ok‎

Lines changed: 113 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,113 @@
1+
[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
2+
[INFO IFP-0001] Added 714 rows of 5263 site FreePDK45_38x28_10R_NP_162NW_34O.
3+
[INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 1000.000 1000.000 ) um
4+
[INFO IFP-0101] Core BBox: ( 0.000 0.000 ) ( 999.970 999.600 ) um
5+
[INFO IFP-0102] Core area: 999570.012 um^2
6+
[INFO IFP-0103] Total instances area: 111.454 um^2
7+
[INFO IFP-0104] Effective utilization: 0.000
8+
[INFO IFP-0105] Number of instances: 68
9+
[INFO RSZ-0026] Removed 5 buffers.
10+
[INFO RSZ-0027] Inserted 9 BUF_X1 input buffers.
11+
[INFO RSZ-0028] Inserted 9 BUF_X1 output buffers.
12+
Found 0 macro blocks.
13+
Using 2 tracks default min distance between IO pins.
14+
[INFO PPL-0001] Number of available slots 12380
15+
[INFO PPL-0002] Number of I/O 19
16+
[INFO PPL-0003] Number of I/O w/sink 19
17+
[INFO PPL-0004] Number of I/O w/o sink 0
18+
[INFO PPL-0005] Slots per section 200
19+
[INFO PPL-0008] Successfully assigned pins to sections.
20+
[INFO PPL-0012] I/O nets HPWL: 1057.01 um.
21+
[INFO GPL-0001] ---- Initialize GPL Main Data Structures
22+
[INFO GPL-0002] DBU: 2000
23+
[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um
24+
[INFO GPL-0004] CoreBBox: ( 0.000 0.000 ) ( 999.970 999.600 ) um
25+
[INFO GPL-0036] Movable instances area: 121.562 um^2
26+
[INFO GPL-0037] Total instances area: 121.562 um^2
27+
[INFO GPL-0035] Pin density area adjust: 7.987 um^2
28+
[INFO GPL-0032] ---- Initialize Region: Top-level
29+
[INFO GPL-0006] Number of instances: 81
30+
[INFO GPL-0007] Movable instances: 81
31+
[INFO GPL-0008] Fixed instances: 0
32+
[INFO GPL-0009] Dummy instances: 0
33+
[INFO GPL-0010] Number of nets: 107
34+
[INFO GPL-0011] Number of pins: 281
35+
[INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 1000.000 1000.000 ) um
36+
[INFO GPL-0013] Core BBox: ( 0.000 0.000 ) ( 999.970 999.600 ) um
37+
[INFO GPL-0016] Core area: 999570.012 um^2
38+
[INFO GPL-0014] Region name: top-level.
39+
[INFO GPL-0015] Region area: 999570.012 um^2
40+
[INFO GPL-0017] Fixed instances area: 0.000 um^2
41+
[INFO GPL-0018] Movable instances area: 129.549 um^2
42+
[INFO GPL-0019] Utilization: 0.013 %
43+
[INFO GPL-0020] Standard cells area: 129.549 um^2
44+
[INFO GPL-0021] Large instances area: 0.000 um^2
45+
[INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement.
46+
[INFO GPL-0051] Source of initial instance position counters:
47+
Odb location = 18 Core center = 63 Region center = 0
48+
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000006 HPWL: 1722700
49+
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000005 HPWL: 8121024
50+
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000011 HPWL: 2164788
51+
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000010 HPWL: 1701248
52+
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000007 HPWL: 1688200
53+
[INFO DPL-0006] Core area: 999570.01 um^2, Instances area: 121.56 um^2, Utilization: 0.0%
54+
[INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically.
55+
[INFO DPL-1101] Legalizing using diamond search.
56+
Movements Summary
57+
---------------------------------------
58+
Total cells: 81
59+
Diamond Move Success: 81 (100.00%)
60+
Diamond Move Failure: 0
61+
Rip-up and replace Success: 0 ( 0.00% of diamond failures)
62+
Rip-up and replace Failure: 0
63+
Total Placement Failures: 0
64+
---------------------------------------
65+
Placement Analysis
66+
---------------------------------
67+
total displacement 798.6 u
68+
average displacement 9.9 u
69+
max displacement 13.0 u
70+
original HPWL 573.2 u
71+
legalized HPWL 1628.1 u
72+
delta HPWL 184 %
73+
74+
[INFO CTS-0050] Root buffer is BUF_X1.
75+
[INFO CTS-0051] Sink buffer is BUF_X1.
76+
[INFO CTS-0052] The following clock buffers will be used for CTS:
77+
BUF_X1
78+
[INFO CTS-0049] Characterization buffer is BUF_X1.
79+
[INFO CTS-0007] Net "clk" found for clock "core".
80+
[INFO CTS-0010] Clock net "clk" has 9 sinks.
81+
[WARNING CTS-0105] Net "clk_out" already has clock buffer output10. Skipping...
82+
[INFO CTS-0008] TritonCTS found 1 clock nets.
83+
[INFO CTS-0097] Characterization used 1 buffer(s) types.
84+
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
85+
[INFO CTS-0027] Generating H-Tree topology for net clk.
86+
[INFO CTS-0028] Total number of sinks: 9.
87+
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
88+
[INFO CTS-0030] Number of static layers: 1.
89+
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
90+
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
91+
[INFO CTS-0023] Original sink region: [(3230, 1230), (10890, 18025)].
92+
[INFO CTS-0024] Normalized sink region: [(0.230714, 0.0878571), (0.777857, 1.2875)].
93+
[INFO CTS-0025] Width: 0.5471.
94+
[INFO CTS-0026] Height: 1.1996.
95+
Level 1
96+
Direction: Vertical
97+
Sinks per sub-region: 5
98+
Sub-region size: 0.5471 X 0.5998
99+
[INFO CTS-0034] Segment length (rounded): 1.
100+
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
101+
[INFO CTS-0035] Number of sinks covered: 9.
102+
[INFO CTS-0018] Created 3 clock buffers.
103+
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
104+
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
105+
[INFO CTS-0015] Created 3 clock nets.
106+
[INFO CTS-0016] Fanout distribution for the current clock = 4:1, 5:1..
107+
[INFO CTS-0017] Max level of the clock tree: 1.
108+
[INFO CTS-0098] Clock net "clk"
109+
[INFO CTS-0099] Sinks 10
110+
[INFO CTS-0100] Leaf buffers 0
111+
[INFO CTS-0101] Average sink wire length 506.70 um
112+
[INFO CTS-0102] Path depth 2 - 2
113+
[INFO CTS-0207] Dummy loads inserted 1

‎src/cts/test/buffer_ports.sdc‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
current_design clk_passthrough_top
2+
set clk_period 500
3+
create_clock -name clk -period $clk_period [get_ports clk]
4+
set_input_delay [expr $clk_period * 0.2] -clock clk [all_inputs -no_clocks]
5+
set_output_delay [expr $clk_period * 0.2] -clock clk [all_outputs]
6+
set_false_path -from [get_ports reset]

‎src/cts/test/buffer_ports.tcl‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
source "helpers.tcl"
2+
3+
source Nangate45/Nangate45.vars
4+
read_liberty Nangate45/Nangate45_typ.lib
5+
read_lef Nangate45/Nangate45.lef
6+
read_verilog buffer_ports.v
7+
8+
link_design clk_passthrough_top
9+
10+
read_sdc buffer_ports.sdc
11+
12+
initialize_floorplan -die_area "0 0 1000 1000" -core_area "0 0 1000 1000" \
13+
-site FreePDK45_38x28_10R_NP_162NW_34O
14+
#make_io_sites -horizontal_site IOSITE -vertical_site IOSITE -corner_site IOSITE -offset 15
15+
source $tracks_file
16+
17+
remove_buffers
18+
buffer_ports
19+
20+
place_pins -hor_layers $io_placer_hor_layer \
21+
-ver_layers $io_placer_ver_layer
22+
global_placement -skip_nesterov_place
23+
detailed_placement
24+
25+
26+
source Nangate45/Nangate45.rc
27+
source $layer_rc_file
28+
set_wire_rc -signal -layer $wire_rc_layer
29+
set_wire_rc -clock -layer $wire_rc_layer_clk
30+
31+
create_clock -name core -period 5 clk
32+
33+
set_debug CTS "insertion delay" 1
34+
35+
clock_tree_synthesis -buf_list BUF_X1 \
36+
-wire_unit 20 \
37+
-sink_clustering_enable \
38+
-distance_between_buffers 100 \
39+
-num_static_layers 1 \
40+
-repair_clock_nets

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