Merge branch 'master' of https://github.com/The-OpenROAD-Project/OpenROAD into grt_cugr_vias

eder-matheus · eder-matheus · commit b18ebbcb4586 · 2026-07-06T14:53:44.000-03:00
diff --git a/BUILD.bazel b/BUILD.bazel
@@ -666,6 +666,7 @@ sh_binary(
         "$(rootpath @buildifier_prebuilt//:buildifier)",
         "$(rootpath //bazel:bzl_lint_test.sh)",
         "$(rootpath @buildifier_prebuilt//:buildifier)",
+        "$(rootpath @git)",
     ],
     data = [
         "MODULE.bazel",
@@ -677,5 +678,6 @@ sh_binary(
         "//bazel:tclfmt",
         "//bazel:tclint",
         "@buildifier_prebuilt//:buildifier",
+        "@git",
     ],
 )
diff --git a/MODULE.bazel b/MODULE.bazel
@@ -159,6 +159,12 @@ archive_override(
 
 bazel_dep(name = "yosys", version = "0.62.bcr.2", dev_dependency = True)
 bazel_dep(name = "yosys-slang", version = "0.0.0", dev_dependency = True)
+archive_override(
+    module_name = "yosys-slang",
+    sha256 = "34198f2ed7b2d3175c3ce3c9fb1c6c91f28dbcfe531d97b91d6b12c48431bdef",
+    strip_prefix = "sv-elab-6760afa2c9b9ba231a9c6a9e94f0939dd39f0a20",
+    urls = ["https://github.com/povik/yosys-slang/archive/6760afa2c9b9ba231a9c6a9e94f0939dd39f0a20.tar.gz"],
+)
 
 # --- Extensions ---
 
diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock
diff --git a/bazel/fix_lint.sh b/bazel/fix_lint.sh
@@ -6,17 +6,27 @@
 # that file-discovery logic is not duplicated (DRY).
 set -euo pipefail
 
+TCL_TIDY_SH="$1"
+TCLFMT="$2"
+TCL_LINT_SH="$3"
+TCLINT="$4"
+BZL_TIDY_SH="$5"
+BZL_FMT_BUILDIFIER="$6"
+BZL_LINT_SH="$7"
+BZL_LINT_BUILDIFIER="$8"
+GIT="$9"
+
 export BUILD_WORKSPACE_DIRECTORY="${BUILD_WORKSPACE_DIRECTORY:-$PWD}"
 
 # TCL: auto-format then lint
-"$1" "$2"
-"$3" "$4" || rc=$?
+"${TCL_TIDY_SH}" "${TCLFMT}"
+"${TCL_LINT_SH}" "${TCLINT}" "${GIT}" || rc=$?
 
 # Bazel: auto-format then lint
-"$5" "$6"
-"$7" "$8" || rc=$?
+"${BZL_TIDY_SH}" "${BZL_FMT_BUILDIFIER}"
+"${BZL_LINT_SH}" "${BZL_LINT_BUILDIFIER}" "${GIT}" || rc=$?
 
-git -C "$BUILD_WORKSPACE_DIRECTORY" status
+"${GIT}" -C "$BUILD_WORKSPACE_DIRECTORY" status
 
 if [ "${rc:-0}" -ne 0 ]; then
     echo "Error: lint violations remain that require manual fixes." >&2
diff --git a/src/Design.cc b/src/Design.cc
@@ -190,7 +190,7 @@ bool Design::isSequential(odb::dbMaster* master)
   if (!lib_cell) {
     return false;
   }
-  return lib_cell->hasSequentials();
+  return lib_cell->isSequential();
 }
 
 bool Design::isInClock(odb::dbInst* inst)
diff --git a/src/cts/src/LatencyBalancer.cpp b/src/cts/src/LatencyBalancer.cpp
@@ -582,7 +582,7 @@ bool LatencyBalancer::propagateClock(odb::dbITerm* input)
     return true;
   }
   // Combinational components
-  if (!libertyCell->hasSequentials()) {
+  if (!libertyCell->isSequential()) {
     return true;
   }
   sta::LibertyPort* inputPort
diff --git a/src/cut/src/abc_library_factory.cpp b/src/cut/src/abc_library_factory.cpp
@@ -78,7 +78,7 @@ static bool IsCombinational(sta::LibertyCell* cell)
     return false;
   }
   return (!cell->isClockGate() && !cell->isPad() && !cell->isMacro()
-          && !cell->hasSequentials() && !cell->isLevelShifter()
+          && !cell->isSequential() && !cell->isLevelShifter()
           && !cell->isIsolationCell() && !cell->isMemory());
 }
 
diff --git a/src/cut/src/blif.cpp b/src/cut/src/blif.cpp
@@ -95,7 +95,7 @@ bool Blif::writeBlif(const char* file_name, bool write_arrival_requireds)
     auto master_name = master->getName();
 
     std::string current_gate
-        = ((cell->hasSequentials()) ? ".mlatch " : ".gate ") + master_name;
+        = ((cell->isSequential()) ? ".mlatch " : ".gate ") + master_name;
     std::string current_connections, current_clock;
     std::set<std::string> current_clocks;
 
@@ -250,10 +250,10 @@ bool Blif::writeBlif(const char* file_name, bool write_arrival_requireds)
 
     current_gate += current_connections;
 
-    if (cell->hasSequentials() && current_clocks.size() != 1) {
+    if (cell->isSequential() && current_clocks.size() != 1) {
       continue;
     }
-    if (cell->hasSequentials()) {
+    if (cell->isSequential()) {
       current_gate += " " + current_clock;
     }
 
diff --git a/src/cut/src/logic_cut.cpp b/src/cut/src/logic_cut.cpp
@@ -212,7 +212,7 @@ void ConnectPinToDriver(
   abc::Abc_Obj_t* abc_net = abc::Abc_NtkCreateNet(&abc_network);
 
   if (network->isTopInstance(driver_instance)
-      || network->libertyCell(driver_instance)->hasSequentials()) {
+      || network->libertyCell(driver_instance)->isSequential()) {
     abc::Abc_Obj_t* abc_input = abc::Abc_NtkCreatePi(&abc_network);
     abc::Abc_ObjAddFanin(abc_net, abc_input);
     std::string driver_name = network->name(driver);
diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc
@@ -5603,7 +5603,7 @@ bool dbNetwork::isValidFlop(odb::dbInst* FF) const
     return false;
   }
   const LibertyCell* lib_cell = testCell(cell);
-  if (lib_cell == nullptr || !lib_cell->hasSequentials()) {
+  if (lib_cell == nullptr || !lib_cell->isSequential()) {
     return false;
   }
 
diff --git a/src/dbSta/src/dbSta.cc b/src/dbSta/src/dbSta.cc
@@ -614,7 +614,7 @@ dbSta::InstType dbSta::getInstanceType(odb::dbInst* inst)
   if (lib_cell->isLevelShifter()) {
     return STD_LEVEL_SHIFT;
   }
-  if (lib_cell->hasSequentials()) {
+  if (lib_cell->isSequential()) {
     return STD_SEQUENTIAL;
   }
   if (lib_cell->portCount() == 0) {
diff --git a/src/dft/src/cells/ScanCellFactory.cpp b/src/dft/src/cells/ScanCellFactory.cpp
@@ -66,7 +66,7 @@ TypeOfCell IdentifyCell(odb::dbInst* inst, sta::dbSta* sta)
   sta::dbNetwork* db_network = sta->getDbNetwork();
   sta::LibertyCell* liberty_cell
       = GetLibertyCell(inst->getMaster(), db_network);
-  if (liberty_cell != nullptr && liberty_cell->hasSequentials()
+  if (liberty_cell != nullptr && liberty_cell->isSequential()
       && !inst->getMaster()->isBlock()) {
     // we assume that we are only dealing with one bit cells, but in the future
     // we could deal with multibit cells too
diff --git a/src/dft/src/replace/ScanReplace.cpp b/src/dft/src/replace/ScanReplace.cpp
@@ -278,7 +278,7 @@ void ScanReplace::collectScanCellAvailable()
       }
 
       // We only care about sequential cells in DFT
-      if (!liberty_cell->hasSequentials()) {
+      if (!liberty_cell->isSequential()) {
         continue;
       }
 
@@ -389,7 +389,7 @@ void ScanReplace::scanReplace(odb::dbBlock* block)
       continue;
     }
 
-    if (!from_liberty_cell->hasSequentials()
+    if (!from_liberty_cell->isSequential()
         || from_liberty_cell->isClockGate()) {
       // If the cell is not sequential, then there is nothing to replace
       continue;
diff --git a/src/dft/src/utils/Utils.cpp b/src/dft/src/utils/Utils.cpp
@@ -54,7 +54,7 @@ bool IsSequentialCell(sta::dbNetwork* db_network, odb::dbInst* instance)
   odb::dbMaster* master = instance->getMaster();
   sta::Cell* master_cell = db_network->dbToSta(master);
   sta::LibertyCell* liberty_cell = db_network->libertyCell(master_cell);
-  return liberty_cell->hasSequentials();
+  return liberty_cell->isSequential();
 }
 
 odb::dbInst* ReplaceCell(
diff --git a/src/est/src/EstimateParasitics.tcl b/src/est/src/EstimateParasitics.tcl
@@ -405,7 +405,7 @@ proc check_corner_wire_caps { } {
   set have_rc 1
   foreach corner [sta::scenes] {
     if { [est::wire_signal_capacitance $corner] == 0.0 } {
-      utl::warn EST 18 "wire capacitance for corner $corner is zero.\
+      utl::warn EST 18 "wire capacitance for corner [get_name $corner] is zero.\
         Use the set_wire_rc command to set wire resistance and capacitance."
       set have_rc 0
     }
diff --git a/src/gpl/src/mbff.cpp b/src/gpl/src/mbff.cpp
@@ -2183,7 +2183,7 @@ bool MBFF::IsValidTray(dbInst* tray)
     return false;
   }
   const sta::LibertyCell* lib_cell = network_->testCell(cell);
-  if (lib_cell == nullptr || !lib_cell->hasSequentials()) {
+  if (lib_cell == nullptr || !lib_cell->isSequential()) {
     return false;
   }
 
diff --git a/src/gui/src/gui.tcl b/src/gui/src/gui.tcl
@@ -173,7 +173,7 @@ proc save_clocktree_image { args } {
     utl::error GUI 88 "-clock is required"
   }
 
-  gui::save_clocktree_image $path $clock $scene $width $height
+  gui::save_clocktree_image $path $clock [get_name $scene] $width $height
 }
 
 sta::define_cmd_args "save_histogram_image" {
diff --git a/src/gui/src/staDescriptors.cpp b/src/gui/src/staDescriptors.cpp
@@ -292,7 +292,7 @@ Descriptor::Properties LibertyCellDescriptor::getProperties(
   }
   add_if_true(props, "Dont Use", cell->dontUse());
   props.push_back({"Filename", cell->filename()});
-  add_if_true(props, "Has Sequentials", cell->hasSequentials());
+  add_if_true(props, "Has Sequentials", cell->isSequential());
   add_if_true(props, "Is Always On", cell->alwaysOn());
   add_if_true(props, "Is Buffer", cell->isBuffer());
   add_if_true(props, "Is Clock Cell", cell->isClockCell());
diff --git a/src/par/src/ArtNetSpec.cpp b/src/par/src/ArtNetSpec.cpp
@@ -157,7 +157,7 @@ void PartitionMgr::getFromODB(
     if (!lib_cell) {
       logger_->error(PAR, 56, "Liberty cell not found: {}", inst->getName());
     }
-    if (lib_cell->hasSequentials()) {
+    if (lib_cell->isSequential()) {
       num_seq++;
     }
     auto [it, inserted]
diff --git a/src/par/src/TritonPart.cpp b/src/par/src/TritonPart.cpp
@@ -1292,7 +1292,7 @@ void TritonPart::ReadNetlist(const std::string& fixed_file,
         vertex_weights_.emplace_back(vwts);
         if (master->isBlock()) {
           vertex_types_.emplace_back(kMacro);
-        } else if (liberty_cell->hasSequentials()) {
+        } else if (liberty_cell->isSequential()) {
           vertex_types_.emplace_back(kSeqStdCell);
         } else {
           vertex_types_.emplace_back(kCombStdCell);
@@ -1336,7 +1336,7 @@ void TritonPart::ReadNetlist(const std::string& fixed_file,
       vertex_weights_.emplace_back(vwts);
       if (master->isBlock()) {
         vertex_types_.emplace_back(kMacro);
-      } else if (liberty_cell->hasSequentials()) {
+      } else if (liberty_cell->isSequential()) {
         vertex_types_.emplace_back(kSeqStdCell);
       } else {
         vertex_types_.emplace_back(kCombStdCell);
diff --git a/src/psm/test/zerosoc_pads.ok b/src/psm/test/zerosoc_pads.ok
@@ -14,11 +14,11 @@ The NOWIREEXTENSIONATPIN statement will be ignored. See file sky130hd_data/io/sk
 ########## IR report #################
 Net              : vdd
 Corner           : default
-Total power      : 8.97e-03 W
+Total power      : 8.80e-03 W
 Supply voltage   : 1.80e+00 V
 Worstcase voltage: 1.80e+00 V
 Average voltage  : 1.80e+00 V
-Average IR drop  : 1.62e-03 V
-Worstcase IR drop: 2.34e-03 V
+Average IR drop  : 1.58e-03 V
+Worstcase IR drop: 2.29e-03 V
 Percentage drop  : 0.13 %
 ######################################
diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp
@@ -748,7 +748,7 @@ void RamGen::findMasters()
             return false;
           }
           auto cell = port->libertyCell();
-          if (!cell->hasSequentials()) {
+          if (!cell->isSequential()) {
             return false;
           }
           bool has_latch_data = false;
diff --git a/src/rmp/src/Restructure.cpp b/src/rmp/src/Restructure.cpp
@@ -450,7 +450,7 @@ void Restructure::removeConstCells()
     auto master = inst->getMaster();
     sta::LibertyCell* cell = open_sta_->getDbNetwork()->libertyCell(
         open_sta_->getDbNetwork()->dbToSta(master));
-    if (cell->hasSequentials()) {
+    if (cell->isSequential()) {
       continue;
     }
 
diff --git a/src/rsz/src/MoveTracker.cc b/src/rsz/src/MoveTracker.cc
@@ -2020,7 +2020,7 @@ void MoveTracker::printTopBinEndpoints(const std::string& title,
       sta::Instance* inst = sta_->network()->instance(pin);
       if (inst) {
         sta::LibertyCell* cell = sta_->network()->libertyCell(inst);
-        if (cell && cell->hasSequentials()) {
+        if (cell && cell->isSequential()) {
           // This is a sequential cell - check if pin is an output
           if (sta_->network()->direction(pin)->isOutput()) {
             startpoint_pin = pin;
diff --git a/src/rsz/src/Resizer.cc b/src/rsz/src/Resizer.cc
@@ -202,7 +202,7 @@ void equivCellPinsForSwapReport(utl::Logger* logger,
                                 sta::LibertyPort* input_port,
                                 LibertyPortVec& ports)
 {
-  if (cell->hasSequentials() || cell->isIsolationCell()) {
+  if (cell->isSequential() || cell->isIsolationCell()) {
     ports.clear();
     return;
   }
@@ -1573,7 +1573,7 @@ bool Resizer::isCombinational(sta::LibertyCell* cell) const
     return false;
   }
   return (!cell->isClockGate() && !cell->isPad() && !cell->isMacro()
-          && !cell->hasSequentials());
+          && !cell->isSequential());
 }
 
 std::vector<sta::LibertyPort*> Resizer::libraryOutputPins(
@@ -3334,7 +3334,7 @@ bool Resizer::isRegister(sta::Vertex* vertex)
   sta::LibertyPort* port = network_->libertyPort(vertex->pin());
   if (port) {
     sta::LibertyCell* cell = port->libertyCell();
-    return cell && cell->hasSequentials();
+    return cell && cell->isSequential();
   }
   return false;
 }
diff --git a/src/rsz/src/move/SizeDownFanoutGenerator.cc b/src/rsz/src/move/SizeDownFanoutGenerator.cc
@@ -423,7 +423,7 @@ SizeDownFanoutOutputProfile buildOutputProfile(
 sta::Slack computeDelayBudget(const SizeDownFanoutContext& ctx,
                               const SizeDownFanoutLoadContext& load_ctx)
 {
-  if (load_ctx.load_cell->hasSequentials()) {
+  if (load_ctx.load_cell->isSequential()) {
     const sta::Slack worst_output_slack
         = getWorstOutputSlack(ctx, load_ctx.load_inst);
     debugPrint(
@@ -514,7 +514,7 @@ float computeWorstDelayChange(const SizeDownFanoutContext& ctx,
     const float new_load_delay = ctx.resizer.gateDelay(
         output_port, profile.output_caps[output_index], ctx.scene, ctx.min_max);
     const float delay_change
-        = load_ctx.load_cell->hasSequentials()
+        = load_ctx.load_cell->isSequential()
               ? new_load_delay - profile.output_delays[output_index]
               : new_load_delay + drvr_delta_delay
                     - profile.output_delays[output_index];
diff --git a/src/rsz/src/move/SwapPinsGenerator.cc b/src/rsz/src/move/SwapPinsGenerator.cc
@@ -210,7 +210,7 @@ void SwapPinsGenerator::equivCellPins(const sta::LibertyCell* cell,
                                       sta::LibertyPort* input_port,
                                       LibertyPortVec& ports) const
 {
-  if (cell->hasSequentials() || cell->isIsolationCell()) {
+  if (cell->isSequential() || cell->isIsolationCell()) {
     ports.clear();
     return;
   }
diff --git a/src/rsz/test/clone_flat.tcl b/src/rsz/test/clone_flat.tcl
@@ -2,7 +2,7 @@
 source "helpers.tcl"
 source "hi_fanout.tcl"
 
-set def_filename [make_result_file "repair_fanout7.def"]
+set def_filename [make_result_file "clone_flat.def"]
 # Gates we want to eventually NAND2_X4, NAND3_X4, NAND4_X4
 
 write_clone_test_def $def_filename NAND2_X4 150
diff --git a/src/rsz/test/repair_fanout7.tcl b/src/rsz/test/repair_fanout7.tcl
@@ -8,6 +8,9 @@ if { ![info exists def_filename] } {
 if { ![info exists repair_args] } {
   set repair_args {}
 }
+if { ![info exists eqy_test_name] } {
+  set eqy_test_name "repair_fanout7"
+}
 # Gates we want to eventually NAND2_X4, NAND3_X4, NAND4_X4
 
 write_clone_test_def $def_filename NAND2_X4 150
@@ -37,9 +40,9 @@ estimate_parasitics -placement
 
 # Repair the high fanout net hopefully with gate cloning code.
 report_worst_slack -max
-write_verilog_for_eqy repair_fanout7 before "None"
+write_verilog_for_eqy $eqy_test_name before "None"
 repair_timing -setup -repair_tns 100 -verbose {*}$repair_args
-run_equivalence_test repair_fanout7 \
+run_equivalence_test $eqy_test_name \
   -lib_dir ./Nangate45/work_around_yosys/ \
   -remove_cells "None"
 report_worst_slack -max
diff --git a/src/rsz/test/repair_fanout7_multi.tcl b/src/rsz/test/repair_fanout7_multi.tcl
@@ -1,4 +1,5 @@
 source "helpers.tcl"
 set def_filename [make_result_file "repair_fanout7_multi.def"]
 set repair_args [list -max_repairs_per_pass 10]
+set eqy_test_name "repair_fanout7_multi"
 source "repair_fanout7.tcl"
diff --git a/src/rsz/test/repair_fanout7_skip_pin_swap.tcl b/src/rsz/test/repair_fanout7_skip_pin_swap.tcl
diff --git a/src/sta b/src/sta
diff --git a/src/syn/src/flow/combinational_mapper.cc b/src/syn/src/flow/combinational_mapper.cc
diff --git a/src/syn/src/flow/liveness.cc b/src/syn/src/flow/liveness.cc
diff --git a/src/syn/src/flow/opt_gatefusion.cc b/src/syn/src/flow/opt_gatefusion.cc
diff --git a/src/syn/src/flow/sequential_mapper.cc b/src/syn/src/flow/sequential_mapper.cc
diff --git a/src/syn/src/ir/Instance.cc b/src/syn/src/ir/Instance.cc
diff --git a/src/syn/src/ir/TritModel.cc b/src/syn/src/ir/TritModel.cc
diff --git a/src/web/src/request_handler.cpp b/src/web/src/request_handler.cpp

Original file line number	Diff line number	Diff line change
`@@ -190,7 +190,7 @@ bool Design::isSequential(odb::dbMaster* master)`
`190`	`190`	`if (!lib_cell) {`
`191`	`191`	`return false;`
`192`	`192`	`}`
`193`		`- return lib_cell->hasSequentials();`
	`193`	`+ return lib_cell->isSequential();`
`194`	`194`	`}`
`195`	`195`
`196`	`196`	`bool Design::isInClock(odb::dbInst* inst)`
Original file line number	Diff line number	Diff line change
`@@ -582,7 +582,7 @@ bool LatencyBalancer::propagateClock(odb::dbITerm* input)`
`582`	`582`	`return true;`
`583`	`583`	`}`
`584`	`584`	`// Combinational components`
`585`		`- if (!libertyCell->hasSequentials()) {`
	`585`	`+ if (!libertyCell->isSequential()) {`
`586`	`586`	`return true;`
`587`	`587`	`}`
`588`	`588`	`sta::LibertyPort* inputPort`
Original file line number	Diff line number	Diff line change
`@@ -78,7 +78,7 @@ static bool IsCombinational(sta::LibertyCell* cell)`
`78`	`78`	`return false;`
`79`	`79`	`}`
`80`	`80`	`return (!cell->isClockGate() && !cell->isPad() && !cell->isMacro()`
`81`		`- && !cell->hasSequentials() && !cell->isLevelShifter()`
	`81`	`+ && !cell->isSequential() && !cell->isLevelShifter()`
`82`	`82`	`&& !cell->isIsolationCell() && !cell->isMemory());`
`83`	`83`	`}`
`84`	`84`
Original file line number	Diff line number	Diff line change
`@@ -5603,7 +5603,7 @@ bool dbNetwork::isValidFlop(odb::dbInst* FF) const`
`5603`	`5603`	`return false;`
`5604`	`5604`	`}`
`5605`	`5605`	`const LibertyCell* lib_cell = testCell(cell);`
`5606`		`- if (lib_cell == nullptr \|\| !lib_cell->hasSequentials()) {`
	`5606`	`+ if (lib_cell == nullptr \|\| !lib_cell->isSequential()) {`
`5607`	`5607`	`return false;`
`5608`	`5608`	`}`
`5609`	`5609`