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eder-matheuseder-matheus
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Merge pull request #10785 from eder-matheus/grt_cugr_logs
grt: add verbose option to CUGR and silence it during incremental
2 parents 7ffde90 + e495a56 commit bb8055a

11 files changed

Lines changed: 130 additions & 32 deletions

‎src/grt/src/GlobalRouter.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,8 @@ std::vector<Net*> GlobalRouter::initCUGR(int min_routing_layer,
217217
}
218218
cugr_->setCriticalNetsPercentage(0);
219219
}
220+
// Set before init so Design::read() gates its statistics on verbosity.
221+
cugr_->setVerbose(verbose_);
220222
cugr_->init(min_routing_layer, max_routing_layer, clock_nets);
221223
return nets;
222224
}
@@ -6341,6 +6343,7 @@ std::vector<Net*> GlobalRouter::updateDirtyRoutes(bool save_guides)
63416343
}
63426344

63436345
if (use_cugr_) {
6346+
cugr_->setVerbose(false);
63446347
for (odb::dbNet* net : dirty_nets_) {
63456348
cugr_->updateNet(net);
63466349
}

‎src/grt/src/cugr/include/CUGR.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,7 @@ class CUGR
117117
{
118118
congestion_iterations_ = iterations;
119119
}
120+
void setVerbose(bool verbose) { verbose_ = verbose; }
120121
void addDirtyNet(odb::dbNet* net);
121122
void updateNet(odb::dbNet* net);
122123
void removeNet(odb::dbNet* net);
@@ -260,6 +261,7 @@ class CUGR
260261

261262
float critical_nets_percentage_ = 10;
262263
int congestion_iterations_ = 5;
264+
bool verbose_ = true;
263265

264266
bool resistance_aware_ = false;
265267
// Per-run normalisers for getResAwareScore (default 1 => well-defined).

‎src/grt/src/cugr/src/CUGR.cpp‎

Lines changed: 24 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,8 @@ void CUGR::init(const int min_routing_layer,
9191
constants_,
9292
min_routing_layer,
9393
max_routing_layer,
94-
clock_nets);
94+
clock_nets,
95+
verbose_);
9596
grid_graph_ = std::make_unique<GridGraph>(design_.get(), constants_, logger_);
9697
// Instantiate the global routing netlist
9798
const std::vector<CUGRNet>& base_nets = design_->getAllNets();
@@ -393,7 +394,9 @@ void CUGR::updateCongestedNets(std::vector<int>& net_indices,
393394

394395
void CUGR::patternRoute(std::vector<int>& net_indices)
395396
{
396-
logger_->report("Stage 1: Pattern routing.");
397+
if (verbose_) {
398+
logger_->report("Stage 1: Pattern routing.");
399+
}
397400

398401
if (critical_nets_percentage_ != 0) {
399402
setInitialNetSlacks();
@@ -434,7 +437,9 @@ void CUGR::patternRouteResAware(std::vector<int>& net_indices)
434437
if (!resistance_aware_ || critical_nets_percentage_ == 0) {
435438
return;
436439
}
437-
logger_->report("Stage 2: Resistance-aware re-route of critical nets.");
440+
if (verbose_) {
441+
logger_->report("Stage 2: Resistance-aware re-route of critical nets.");
442+
}
438443

439444
// Stage 1 routed neutrally, so real 3D trees now exist; mark the res-aware
440445
// set from their actual per-net resistance.
@@ -496,7 +501,9 @@ void CUGR::patternRouteWithDetours(std::vector<int>& net_indices)
496501
if (net_indices.empty()) {
497502
return;
498503
}
499-
logger_->report("Stage 3: Pattern routing with detours.");
504+
if (verbose_) {
505+
logger_->report("Stage 3: Pattern routing with detours.");
506+
}
500507

501508
if (critical_nets_percentage_ != 0) {
502509
updateCriticalNets();
@@ -623,7 +630,7 @@ void CUGR::route()
623630

624631
patternRouteWithDetours(net_indices);
625632

626-
if (!net_indices.empty()) {
633+
if (verbose_ && !net_indices.empty()) {
627634
logger_->report("Stage 4: Maze routing on sparsified graph.");
628635
}
629636
mazeRoute(net_indices);
@@ -739,7 +746,9 @@ void CUGR::iterativeRRR(std::vector<int>& net_indices)
739746
return;
740747
}
741748

742-
logger_->report("Stage 5: Iterative rip-up and re-route.");
749+
if (verbose_) {
750+
logger_->report("Stage 5: Iterative rip-up and re-route.");
751+
}
743752

744753
// Multiplier ramps up to saturate around slope=6 — beyond that the
745754
// logistic cost surface degenerates into a step function with no
@@ -807,12 +816,14 @@ void CUGR::iterativeRRR(std::vector<int>& net_indices)
807816
multiplier += kMultiplierStep;
808817
}
809818
grid_graph_->setCostMultiplier(multiplier);
810-
logger_->info(
811-
GRT, 117, "Start extra iteration {}/{}", i, congestion_iterations_);
819+
if (verbose_) {
820+
logger_->info(
821+
GRT, 117, "Start extra iteration {}/{}", i, congestion_iterations_);
822+
}
812823
mazeRoute(net_indices);
813824
}
814825
grid_graph_->setCostMultiplier(1.0);
815-
if (soft_ndr_demotions > 0) {
826+
if (verbose_ && soft_ndr_demotions > 0) {
816827
logger_->info(GRT,
817828
306,
818829
"Iterative RRR soft-demoted {} NDR net(s) total.",
@@ -1077,6 +1088,10 @@ void CUGR::getGuides(const GRNet* net,
10771088

10781089
void CUGR::printStatistics() const
10791090
{
1091+
if (!verbose_) {
1092+
return;
1093+
}
1094+
10801095
logger_->report("Routing statistics");
10811096

10821097
// wire length and via count

‎src/grt/src/cugr/src/Design.cpp‎

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -24,14 +24,16 @@ Design::Design(odb::dbDatabase* db,
2424
const Constants& constants,
2525
const int min_routing_layer,
2626
const int max_routing_layer,
27-
const odb::PtrSet<odb::dbNet>& clock_nets)
27+
const odb::PtrSet<odb::dbNet>& clock_nets,
28+
const bool verbose)
2829
: block_(db->getChip()->getBlock()),
2930
tech_(db->getTech()),
3031
logger_(logger),
3132
constants_(constants),
3233
min_routing_layer_(min_routing_layer),
3334
max_routing_layer_(max_routing_layer),
34-
clock_nets_(clock_nets)
35+
clock_nets_(clock_nets),
36+
verbose_(verbose)
3537
{
3638
read();
3739
setUnitCosts();
@@ -55,10 +57,12 @@ void Design::read()
5557

5658
computeGrid();
5759

58-
logger_->report("Design statistics");
59-
logger_->report("Nets: {}", nets_.size());
60-
logger_->report("Special nets: {}", num_special_nets);
61-
logger_->report("Routing layers: {}", getNumLayers());
60+
if (verbose_) {
61+
logger_->report("Design statistics");
62+
logger_->report("Nets: {}", nets_.size());
63+
logger_->report("Special nets: {}", num_special_nets);
64+
logger_->report("Routing layers: {}", getNumLayers());
65+
}
6266
}
6367

6468
void Design::readLayers()

‎src/grt/src/cugr/src/Design.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,8 @@ class Design
4040
const Constants& constants,
4141
int min_routing_layer,
4242
int max_routing_layer,
43-
const odb::PtrSet<odb::dbNet>& clock_nets);
43+
const odb::PtrSet<odb::dbNet>& clock_nets,
44+
bool verbose);
4445
int getLibDBU() const { return lib_dbu_; }
4546

4647
CostT getUnitLengthWireCost() const { return unit_length_wire_cost_; }
@@ -113,6 +114,7 @@ class Design
113114
const int min_routing_layer_;
114115
const int max_routing_layer_;
115116
odb::PtrSet<odb::dbNet> clock_nets_;
117+
const bool verbose_;
116118
};
117119

118120
} // namespace grt

‎src/grt/test/incremental_deleted_net.ok‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -64,12 +64,5 @@ Total 7828 47 0.60% 0 / 0 / 0
6464

6565
[INFO GRT-0018] Total wirelength: 319 um
6666
[INFO GRT-0014] Routed nets: 5
67-
Stage 1: Pattern routing.
68-
Routing statistics
69-
Wire length: 709
70-
Total via count: 28
71-
Total congestion: 0
72-
Min resource: 1.5
73-
Bottleneck: (6, 0, 0)
7467
Summary 1 / 1 (100% pass)
7568
pass

‎src/grt/test/incremental_update_net.ok‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -65,12 +65,5 @@ Total 7828 47 0.60% 0 / 0 / 0
6565

6666
[INFO GRT-0018] Total wirelength: 319 um
6767
[INFO GRT-0014] Routed nets: 5
68-
Stage 1: Pattern routing.
69-
Routing statistics
70-
Wire length: 709
71-
Total via count: 28
72-
Total congestion: 0
73-
Min resource: 1.5
74-
Bottleneck: (6, 0, 0)
7568
Summary 1 / 1 (100% pass)
7669
pass

‎src/grt/test/resistance_aware_asap7_cong_cugr.ok‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,10 +38,38 @@
3838
[INFO ODB-0130] Created 54 pins.
3939
[INFO ODB-0131] Created 470 components and 2159 component-terminals.
4040
[INFO ODB-0133] Created 416 nets and 1216 connections.
41+
[INFO GRT-0020] Min routing layer: M2
42+
[INFO GRT-0021] Max routing layer: M6
43+
[INFO GRT-0022] Global adjustment: 0%
44+
[INFO GRT-0023] Grid origin: (0, 0)
45+
[INFO GRT-0088] Layer M1 Track-Pitch = 0.0360 line-2-Via Pitch: 0.0360
46+
[INFO GRT-0088] Layer M2 Track-Pitch = 0.0390 line-2-Via Pitch: 0.0360
47+
[INFO GRT-0088] Layer M3 Track-Pitch = 0.0360 line-2-Via Pitch: 0.0360
48+
[INFO GRT-0088] Layer M4 Track-Pitch = 0.0480 line-2-Via Pitch: 0.0480
49+
[INFO GRT-0088] Layer M5 Track-Pitch = 0.0480 line-2-Via Pitch: 0.0480
50+
[INFO GRT-0088] Layer M6 Track-Pitch = 0.0640 line-2-Via Pitch: 0.0640
51+
[INFO GRT-0003] Macros: 0
52+
[INFO GRT-0004] Blockages: 105
53+
[INFO GRT-0019] Found 6 clock nets.
54+
[INFO GRT-0001] Minimum degree: 2
55+
[INFO GRT-0002] Maximum degree: 57
4156
Design statistics
4257
Nets: 416
4358
Special nets: 0
4459
Routing layers: 6
60+
61+
[INFO GRT-0053] Routing resources analysis:
62+
Routing Original Derated Resource
63+
Layer Direction Resources Resources Reduction (%)
64+
---------------------------------------------------------------
65+
M1 Vertical 0 0 0.00%
66+
M2 Horizontal 445866 178347 60.00%
67+
M3 Vertical 483372 193349 60.00%
68+
M4 Horizontal 362442 144977 60.00%
69+
M5 Vertical 362442 144977 60.00%
70+
M6 Horizontal 271962 108785 60.00%
71+
---------------------------------------------------------------
72+
4573
Stage 1: Pattern routing.
4674
Stage 2: Resistance-aware re-route of critical nets.
4775
Stage 3: Pattern routing with detours.
@@ -51,6 +79,21 @@ Total via count: 2488
5179
Total congestion: 0
5280
Min resource: 0.07543831038893245
5381
Bottleneck: (4, 88, 152)
82+
83+
[INFO GRT-0096] Final congestion report:
84+
Layer Resource Demand Usage (%) Max H / Max V / Total Congestion
85+
---------------------------------------------------------------------------------------
86+
M1 0 0 0.00% 0 / 0 / 0
87+
M2 178347 538 0.30% 0 / 0 / 0
88+
M3 193349 1054 0.55% 0 / 0 / 0
89+
M4 144977 333 0.23% 0 / 0 / 0
90+
M5 144977 671 0.46% 0 / 0 / 0
91+
M6 108785 119 0.11% 0 / 0 / 0
92+
---------------------------------------------------------------------------------------
93+
Total 770435 2715 0.35% 0 / 0 / 0
94+
95+
[INFO GRT-0018] Total wirelength: 1827 um
96+
[INFO GRT-0014] Routed nets: 416
5497
baseline (no resistance-aware) WNS: -122.0 ps TNS: -2912.8 ps
5598
resistance-aware WNS: -121.4 ps TNS: -2848.8 ps
5699
resistance-aware WNS and TNS not worse than baseline: PASS

‎src/grt/test/resistance_aware_asap7_cong_cugr.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ set guide_file [make_result_file resistance_aware_asap7_cong_cugr.guide]
5454
set_routing_layers -signal M2-M6 -clock M4-M6
5555
set_global_routing_layer_adjustment M2-M7 0.6
5656

57-
global_route -use_cugr -critical_nets_percentage 30 -resistance_aware
57+
global_route -use_cugr -critical_nets_percentage 30 -resistance_aware -verbose
5858

5959
write_guides $guide_file
6060

‎src/grt/test/resistance_aware_asap7_cugr.ok‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,10 +38,38 @@
3838
[INFO ODB-0130] Created 54 pins.
3939
[INFO ODB-0131] Created 470 components and 2159 component-terminals.
4040
[INFO ODB-0133] Created 416 nets and 1216 connections.
41+
[INFO GRT-0020] Min routing layer: M2
42+
[INFO GRT-0021] Max routing layer: M6
43+
[INFO GRT-0022] Global adjustment: 0%
44+
[INFO GRT-0023] Grid origin: (0, 0)
45+
[INFO GRT-0088] Layer M1 Track-Pitch = 0.0360 line-2-Via Pitch: 0.0360
46+
[INFO GRT-0088] Layer M2 Track-Pitch = 0.0390 line-2-Via Pitch: 0.0360
47+
[INFO GRT-0088] Layer M3 Track-Pitch = 0.0360 line-2-Via Pitch: 0.0360
48+
[INFO GRT-0088] Layer M4 Track-Pitch = 0.0480 line-2-Via Pitch: 0.0480
49+
[INFO GRT-0088] Layer M5 Track-Pitch = 0.0480 line-2-Via Pitch: 0.0480
50+
[INFO GRT-0088] Layer M6 Track-Pitch = 0.0640 line-2-Via Pitch: 0.0640
51+
[INFO GRT-0003] Macros: 0
52+
[INFO GRT-0004] Blockages: 105
53+
[INFO GRT-0019] Found 6 clock nets.
54+
[INFO GRT-0001] Minimum degree: 2
55+
[INFO GRT-0002] Maximum degree: 57
4156
Design statistics
4257
Nets: 416
4358
Special nets: 0
4459
Routing layers: 6
60+
61+
[INFO GRT-0053] Routing resources analysis:
62+
Routing Original Derated Resource
63+
Layer Direction Resources Resources Reduction (%)
64+
---------------------------------------------------------------
65+
M1 Vertical 0 0 0.00%
66+
M2 Horizontal 445866 334400 25.00%
67+
M3 Vertical 483372 362529 25.00%
68+
M4 Horizontal 362442 271832 25.00%
69+
M5 Vertical 362442 271832 25.00%
70+
M6 Horizontal 271962 203972 25.00%
71+
---------------------------------------------------------------
72+
4573
Stage 1: Pattern routing.
4674
Stage 2: Resistance-aware re-route of critical nets.
4775
Routing statistics
@@ -50,6 +78,21 @@ Total via count: 2223
5078
Total congestion: 0
5179
Min resource: 3.378947368421052
5280
Bottleneck: (4, 88, 153)
81+
82+
[INFO GRT-0096] Final congestion report:
83+
Layer Resource Demand Usage (%) Max H / Max V / Total Congestion
84+
---------------------------------------------------------------------------------------
85+
M1 0 0 0.00% 0 / 0 / 0
86+
M2 334400 635 0.19% 0 / 0 / 0
87+
M3 362529 1129 0.31% 0 / 0 / 0
88+
M4 271832 137 0.05% 0 / 0 / 0
89+
M5 271832 577 0.21% 0 / 0 / 0
90+
M6 203972 168 0.08% 0 / 0 / 0
91+
---------------------------------------------------------------------------------------
92+
Total 1444565 2646 0.18% 0 / 0 / 0
93+
94+
[INFO GRT-0018] Total wirelength: 1825 um
95+
[INFO GRT-0014] Routed nets: 416
5396
baseline (no resistance-aware) WNS: -121.9 ps TNS: -2892.8 ps
5497
resistance-aware WNS: -121.6 ps TNS: -2846.6 ps
5598
resistance-aware WNS and TNS not worse than baseline: PASS

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