rsz: Optimize latch time-borrow setup paths

Treat positive latch time borrowing as hidden setup debt when collecting and repairing setup endpoints. This lets repair_timing optimize paths that report zero slack only because latch transparency is fully consumed.\n\nUse effective endpoint slack during legacy setup repair and accept endpoint improvement when global WNS is unchanged. Add an inferred clock gator regression that verifies repair_timing reduces latch borrow on the enable path.\n\nTesting:\n- cmake --build tools/OpenROAD/build --target openroad -j64\n- ctest --test-dir tools/OpenROAD/build -R '^rsz\.inferred_clock_gator_time_borrow\.tcl$' --output-on-failure

Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

Author: jhkim-pii

src/rsz/src/RepairTargetCollector.cc

@@ -812,9 +812,9 @@ void RepairTargetCollector::collectViolatingEndpoints()
 
   const sta::VertexSet& endpoints = sta_->endpoints();
   for (sta::Vertex* endpoint : endpoints) {
-    const sta::Slack endpoint_slack = sta_->slack(endpoint, max_);
-    if (sta::fuzzyLess(endpoint_slack, slack_margin_)) {
-      violating_endpoints_.emplace_back(endpoint->pin(), endpoint_slack);
+    const sta::Slack effective_slack = getEndpointEffectiveSlack(endpoint);
+    if (sta::fuzzyLess(effective_slack, slack_margin_)) {
+      violating_endpoints_.emplace_back(endpoint->pin(), effective_slack);
     }
   }
 
@@ -832,6 +832,55 @@ void RepairTargetCollector::collectViolatingEndpoints()
                  * 100));
 }
 
+sta::Slack RepairTargetCollector::getEndpointEffectiveSlack(
+    sta::Vertex* endpoint) const
+{
+  const sta::Slack reported_slack = sta_->slack(endpoint, max_);
+  if (sta::fuzzyGreater(reported_slack, slack_margin_)) {
+    return reported_slack;
+  }
+
+  sta::PinSet* to_pins = new sta::PinSet(network_);
+  to_pins->insert(endpoint->pin());
+  sta::ExceptionTo* to = sdc_->makeExceptionTo(to_pins,
+                                               nullptr,
+                                               nullptr,
+                                               sta::RiseFallBoth::riseFall(),
+                                               sta::RiseFallBoth::riseFall());
+
+  sta::StringSeq group_names;
+  sta::PathEndSeq path_ends
+      = search_->findPathEnds(nullptr,                // from
+                              nullptr,                // thrus
+                              to,                     // to
+                              false,                  // unconstrained
+                              sta_->scenes(),         // scene
+                              sta::MinMaxAll::max(),  // min_max
+                              1,                      // group_path_count
+                              1,                      // endpoint_path_count
+                              false,                  // unique_pins
+                              false,                  // unique_edges
+                              -sta::INF,              // slack_min
+                              sta::INF,               // slack_max
+                              true,                   // sort_by_slack
+                              group_names,            // group_names
+                              true,
+                              false,
+                              true,
+                              true,
+                              true,
+                              true);  // checks
+
+  if (path_ends.empty()) {
+    return reported_slack;
+  }
+
+  // Treat consumed latch transparency as hidden setup debt for repair_timing.
+  // Only positive borrow adds debt; flop endpoints report zero borrow.
+  const sta::Arrival borrow = path_ends[0]->borrow(search_);
+  return reported_slack - std::max<float>(borrow, 0.0f);
+}
+
 void RepairTargetCollector::collectViolatingStartpoints()
 {
   violating_startpoints_.clear();

src/rsz/src/RepairTargetCollector.hh

@@ -169,6 +169,10 @@ class RepairTargetCollector
 
   // Public endpoint collection for TNS Phase
   void collectViolatingEndpoints();
+  // Effective slack includes hidden setup debt from latch time borrowing.
+  // A latch endpoint with reported slack of zero but positive borrow is treated
+  // as a setup violation by subtracting the borrow from the reported slack.
+  sta::Slack getEndpointEffectiveSlack(sta::Vertex* endpoint) const;
   sta::Slack getPathSlackByIndex(const sta::Pin* endpoint_pin, int path_index);
   const vector<std::pair<const sta::Pin*, sta::Slack>>& getViolatingEndpoints()
       const

src/rsz/src/policy/SetupLegacyBase.cc

@@ -95,7 +95,8 @@ bool SetupLegacyBase::repairSetupPin(const sta::Pin* end_pin)
     return false;
   }
 
-  const sta::Slack end_slack = sta_->slack(end_vertex, max_);
+  const sta::Slack end_slack
+      = target_collector_->getEndpointEffectiveSlack(end_vertex);
   sta::Path* end_path = sta_->vertexWorstSlackPath(end_vertex, max_);
   if (end_path == nullptr) {
     return false;
@@ -299,7 +300,8 @@ void SetupLegacyBase::saveImprovedCheckpoint(
 void SetupLegacyBase::refreshEndpointSlacks(
     SetupLegacyBase::EndpointRepairState& endpoint_state)
 {
-  endpoint_state.end_slack = sta_->slack(endpoint_state.end, max_);
+  endpoint_state.end_slack
+      = target_collector_->getEndpointEffectiveSlack(endpoint_state.end);
   sta_->worstSlack(
       max_, endpoint_state.worst_slack, endpoint_state.worst_vertex);
 }

src/rsz/src/policy/SetupLegacyPolicy.cc

@@ -238,8 +238,7 @@ void SetupLegacyPolicy::repairEndpoint(EndpointRepairState& endpoint_state,
     refreshEndpointSlacks(endpoint_state);
 
     // Promote only the passes that improve the tracked objective.
-    const bool better = pathImproved(main_state.end_index,
-                                     endpoint_state.end_slack,
+    const bool better = pathImproved(endpoint_state.end_slack,
                                      endpoint_state.worst_slack,
                                      endpoint_state.prev_end_slack,
                                      endpoint_state.prev_worst_slack);
@@ -394,14 +393,13 @@ void SetupLegacyPolicy::runMainRepairLoop(const ViolatingEnds& violating_ends,
   }
 }
 
-bool SetupLegacyPolicy::pathImproved(const int end_index,
-                                     const sta::Slack end_slack,
+bool SetupLegacyPolicy::pathImproved(const sta::Slack end_slack,
                                      const sta::Slack worst_slack,
                                      const sta::Slack prev_end_slack,
                                      const sta::Slack prev_worst_slack) const
 {
   return sta::fuzzyGreater(worst_slack, prev_worst_slack)
-         || (end_index != 1 && sta::fuzzyEqual(worst_slack, prev_worst_slack)
+         || (sta::fuzzyEqual(worst_slack, prev_worst_slack)
              && sta::fuzzyGreater(end_slack, prev_end_slack));
 }
 

src/rsz/src/policy/SetupLegacyPolicy.hh

@@ -56,8 +56,7 @@ class SetupLegacyPolicy : public SetupLegacyBase
   {
     return "LEGACY Phase Endpoint Profiler";
   }
-  bool pathImproved(int end_index,
-                    sta::Slack end_slack,
+  bool pathImproved(sta::Slack end_slack,
                     sta::Slack worst_slack,
                     sta::Slack prev_end_slack,
                     sta::Slack prev_worst_slack) const;

src/rsz/test/BUILD

@@ -257,6 +257,7 @@ PASSFAIL_TESTS = [
     # NOTE: cpp_tests excluded - it's a CMake-specific wrapper script that expects
     # build directory structure not compatible with Bazel
     # "cpp_tests",
+    "inferred_clock_gator_time_borrow",
     "repair_setup_legacy_mt",
     "repair_setup_mt1",
 ]

src/rsz/test/CMakeLists.txt

@@ -239,6 +239,7 @@ or_integration_tests(
     global_sizing_threads
     global_sizing_presize
   PASSFAIL_TESTS
+    inferred_clock_gator_time_borrow
     repair_setup_legacy_mt
     repair_setup_mt1
     cpp_tests

src/rsz/test/inferred_clock_gator_time_borrow.def

@@ -0,0 +1,70 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN inferred_clock_gator_time_borrow ;
+UNITS DISTANCE MICRONS 2000 ;
+
+DIEAREA ( 0 0 ) ( 240000 240000 ) ;
+
+COMPONENTS 10 ;
+- enable_buf0 BUF_X1 + PLACED ( 40000 120000 ) N ;
+- enable_buf1 BUF_X1 + PLACED ( 80000 120000 ) N ;
+- enable_latch DLL_X1 + PLACED ( 89540 158990 ) N ;
+- inferred_gate AND2_X1 + PLACED ( 88400 89470 ) N ;
+- sibling_branch CLKBUF_X3 + PLACED ( 91580 89470 ) N ;
+- sibling_ff0 DFF_X1 + PLACED ( 139840 89510 ) N ;
+- gated_ff0 DFF_X1 + PLACED ( 159600 158985 ) N ;
+- gated_ff1 DFF_X1 + PLACED ( 167580 158985 ) N ;
+- gated_ff2 DFF_X1 + PLACED ( 159600 167045 ) N ;
+- gated_ff3 DFF_X1 + PLACED ( 167580 167045 ) N ;
+END COMPONENTS
+
+PINS 2 ;
+- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+  + LAYER metal6 ( -140 0 ) ( 140 280 ) + FIXED ( 120000 240000 ) S ;
+- en_in + NET en_in + DIRECTION INPUT + USE SIGNAL
+  + LAYER metal6 ( -140 0 ) ( 140 280 ) + FIXED ( 0 120000 ) W ;
+END PINS
+
+NETS 7 ;
+- clk
+  ( PIN clk )
+  ( enable_latch GN )
+  ( inferred_gate A1 )
+  ( sibling_branch A )
+  + USE SIGNAL ;
+- en_in
+  ( PIN en_in )
+  ( enable_buf0 A )
+  + USE SIGNAL ;
+- en_mid0
+  ( enable_buf0 Z )
+  ( enable_buf1 A )
+  + USE SIGNAL ;
+- en_mid1
+  ( enable_buf1 Z )
+  ( enable_latch D )
+  + USE SIGNAL ;
+- en_lat
+  ( enable_latch Q )
+  ( inferred_gate A2 )
+  ( sibling_ff0 D )
+  ( gated_ff0 D )
+  ( gated_ff1 D )
+  ( gated_ff2 D )
+  ( gated_ff3 D )
+  + USE SIGNAL ;
+- sibling_clk
+  ( sibling_branch Z )
+  ( sibling_ff0 CK )
+  + USE SIGNAL ;
+- gated_clk
+  ( inferred_gate ZN )
+  ( gated_ff0 CK )
+  ( gated_ff1 CK )
+  ( gated_ff2 CK )
+  ( gated_ff3 CK )
+  + USE SIGNAL ;
+END NETS
+
+END DESIGN

src/rsz/test/inferred_clock_gator_time_borrow.ok

@@ -0,0 +1,162 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0128] Design: inferred_clock_gator_time_borrow
+[INFO ODB-0130]     Created 2 pins.
+[INFO ODB-0131]     Created 10 components and 52 component-terminals.
+[INFO ODB-0133]     Created 7 nets and 22 connections.
+[INFO CTS-0050] Root buffer is CLKBUF_X3.
+[INFO CTS-0051] Sink buffer is CLKBUF_X3.
+[INFO CTS-0052] The following clock buffers will be used for CTS:
+                    CLKBUF_X3
+[INFO CTS-0049] Characterization buffer is CLKBUF_X3.
+[INFO CTS-0007] Net "clk" found for clock "clk".
+[INFO CTS-0011]  Clock net "clk" for macros has 2 sinks.
+[INFO CTS-0011]  Clock net "clk_regs" for registers has 1 sinks.
+[INFO CTS-0010]  Clock net "gated_clk" has 4 sinks.
+[WARNING CTS-0041] Net "sibling_clk" has 1 sinks. Skipping...
+[INFO CTS-0008] TritonCTS found 3 clock nets.
+[INFO CTS-0097] Characterization used 1 buffer(s) types.
+[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
+[INFO CTS-0027] Generating H-Tree topology for net clk.
+[INFO CTS-0028]  Total number of sinks: 2.
+[INFO CTS-0060]  Macro  sinks will be clustered in groups of up to 4 and based on buffer max cap.
+[INFO CTS-0030]  Number of static layers: 1.
+[INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
+[INFO CTS-0021]  Distance between buffers: 5 units (80 um).
+[INFO CTS-0023]  Original sink region: [(91830, 90695), (167065, 165470)].
+[INFO CTS-0024]  Normalized sink region: [(6.55929, 6.47821), (11.9332, 11.8193)].
+[INFO CTS-0025]     Width:  5.3739.
+[INFO CTS-0026]     Height: 5.3411.
+ Level 1
+    Direction: Horizontal
+    Sinks per sub-region: 1
+    Sub-region size: 2.6870 X 5.3411
+[INFO CTS-0034]     Segment length (rounded): 1.
+[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
+[INFO CTS-0035]  Number of sinks covered: 2.
+[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
+[INFO CTS-0027] Generating H-Tree topology for net clk_regs.
+[INFO CTS-0028]  Total number of sinks: 1.
+[INFO CTS-0090]  Sinks will be clustered based on buffer max cap.
+[INFO CTS-0030]  Number of static layers: 1.
+[INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
+[INFO CTS-0021]  Distance between buffers: 5 units (80 um).
+[INFO CTS-0023]  Original sink region: [(92825, 160215), (92825, 160215)].
+[INFO CTS-0024]  Normalized sink region: [(6.63036, 11.4439), (6.63036, 11.4439)].
+[INFO CTS-0025]     Width:  0.0000.
+[INFO CTS-0026]     Height: 0.0000.
+ Level 1
+    Direction: Vertical
+    Sinks per sub-region: 1
+    Sub-region size: 0.0000 X 0.0000
+[INFO CTS-0034]     Segment length (rounded): 1.
+[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
+[INFO CTS-0035]  Number of sinks covered: 1.
+[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
+[INFO CTS-0027] Generating H-Tree topology for net gated_clk.
+[INFO CTS-0028]  Total number of sinks: 4.
+[INFO CTS-0090]  Sinks will be clustered based on buffer max cap.
+[INFO CTS-0030]  Number of static layers: 1.
+[INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
+[INFO CTS-0021]  Distance between buffers: 5 units (80 um).
+[INFO CTS-0023]  Original sink region: [(162830, 160215), (170810, 168275)].
+[INFO CTS-0024]  Normalized sink region: [(11.6307, 11.4439), (12.2007, 12.0196)].
+[INFO CTS-0025]     Width:  0.5700.
+[INFO CTS-0026]     Height: 0.5757.
+ Level 1
+    Direction: Vertical
+    Sinks per sub-region: 2
+    Sub-region size: 0.5700 X 0.2879
+[INFO CTS-0034]     Segment length (rounded): 1.
+[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
+[INFO CTS-0035]  Number of sinks covered: 4.
+[INFO CTS-0018]     Created 3 clock buffers.
+[INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
+[INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
+[INFO CTS-0015]     Created 3 clock nets.
+[INFO CTS-0016]     Fanout distribution for the current clock = 1:2..
+[INFO CTS-0017]     Max level of the clock tree: 1.
+[INFO CTS-0018]     Created 2 clock buffers.
+[INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
+[INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
+[INFO CTS-0015]     Created 2 clock nets.
+[INFO CTS-0016]     Fanout distribution for the current clock = 1:1..
+[INFO CTS-0017]     Max level of the clock tree: 1.
+[INFO CTS-0018]     Created 3 clock buffers.
+[INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
+[INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
+[INFO CTS-0015]     Created 3 clock nets.
+[INFO CTS-0016]     Fanout distribution for the current clock = 2:2..
+[INFO CTS-0017]     Max level of the clock tree: 1.
+[INFO CTS-0098] Clock net "clk"
+[INFO CTS-0099]  Sinks 2
+[INFO CTS-0100]  Leaf buffers 0
+[INFO CTS-0101]  Average sink wire length 97.63 um
+[INFO CTS-0102]  Path depth 2 - 2
+[INFO CTS-0207]  Dummy loads inserted 1
+[INFO CTS-0124] Clock net "clk_regs"
+[INFO CTS-0125]  Sinks 1
+[INFO CTS-0098] Clock net "gated_clk"
+[INFO CTS-0099]  Sinks 4
+[INFO CTS-0100]  Leaf buffers 0
+[INFO CTS-0101]  Average sink wire length 15.14 um
+[INFO CTS-0102]  Path depth 2 - 2
+[INFO CTS-0207]  Dummy loads inserted 0
+[INFO CTS-0033] Balancing latency for clock clk
+[INFO CTS-0036]  inserted 4 delay buffers
+[INFO CTS-0037] Total number of delay buffers: 4
+[WARNING STA-0450] virtual clock vclk can not be propagated.
+BEFORE_BORROW 0.4005
+[INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove BufferMove SplitLoadMove 
+[INFO RSZ-0094] Found 7 endpoints with setup violations.
+[INFO RSZ-0099] Repairing 7 out of 7 (100.00%) violating endpoints...
+   Iter   | Removed | Resized | Inserted | Cloned |  Pin  |   Area   |    WNS   |   StTNS    |   EnTNS    |  Viol  |  Worst  
+          | Buffers |  Gates  | Buffers  |  Gates | Swaps |          |          |            |            | Endpts | St/EnPt 
+------------------------------------------------------------------------------------------------------------------------------
+       0* |       0 |       0 |        0 |      0 |     0 |    +0.0% |   -0.055 |       -0.1 |       -0.1 |      7 | inferred_gate/A2
+      21* |       1 |       1 |        3 |      0 |     0 |    +3.9% |   -0.027 |       -0.0 |       -0.1 |      7 | inferred_gate/A2
+    final |       1 |       1 |        3 |      0 |     0 |    +3.9% |   -0.027 |       -0.0 |       -0.1 |      7 | inferred_gate/A2
+------------------------------------------------------------------------------------------------------------------------------
+[INFO RSZ-0059] Removed 1 buffers.
+[INFO RSZ-0040] Inserted 3 buffers.
+[INFO RSZ-0051] Resized 1 instances: 1 up, 0 up match, 0 down, 0 VT
+[WARNING RSZ-0062] Unable to repair all setup violations.
+AFTER_BORROW 0.3769
+Startpoint: enable_latch (negative level-sensitive latch clocked by clk)
+Endpoint: inferred_gate (rising clock gating-check end-point clocked by clk)
+Path Group: gated clock
+Path Type: max
+
+    Delay      Time   Description
+-------------------------------------------------------------
+   0.5000    0.5000   clock clk (fall edge)
+   0.0000    0.5000   clock source latency
+   0.0000    0.5000 v clk (in)
+   0.0248    0.5248 v delaybuf_2_clk/Z (CLKBUF_X3)
+   0.0278    0.5525 v delaybuf_3_clk/Z (CLKBUF_X3)
+   0.0261    0.5787 v clkbuf_regs_0_clk/Z (CLKBUF_X3)
+   0.0263    0.6049 v clkbuf_0_clk_regs/Z (CLKBUF_X3)
+   0.0259    0.6309 v clkbuf_1_0__f_clk_regs/Z (CLKBUF_X3)
+   0.0000    0.6309 v enable_latch/GN (DLL_X2)
+   0.3769    1.0078   time given to startpoint
+   0.0000    1.0078 v enable_latch/D (DLL_X2)
+   0.0731    1.0809 v enable_latch/Q (DLL_X2)
+   0.0007    1.0815 v inferred_gate/A2 (AND2_X1)
+             1.0815   data arrival time
+
+   1.0000    1.0000   clock clk (rise edge)
+   0.0000    1.0000   clock source latency
+   0.0000    1.0000 ^ clk (in)
+   0.0255    1.0255 ^ clkbuf_0_clk/Z (CLKBUF_X3)
+   0.0292    1.0547 ^ clkbuf_1_1__f_clk/Z (CLKBUF_X3)
+   0.0001    1.0548 ^ inferred_gate/A1 (AND2_X1)
+   0.0000    1.0548   clock reconvergence pessimism
+   0.0000    1.0548   clock gating setup time
+             1.0548   data required time
+-------------------------------------------------------------
+             1.0548   data required time
+            -1.0815   data arrival time
+-------------------------------------------------------------
+            -0.0268   slack (VIOLATED)
+
+
+pass inferred_clock_gator_time_borrow