cts: update buffer ports ok

Signed-off-by: arthurjolo <arthurjl@precisioninno.com>

Author: arthurjolo

src/cts/test/buffer_ports.ok

@@ -17,7 +17,7 @@ Using 2 tracks default min distance between IO pins.
 [INFO PPL-0004] Number of I/O w/o sink    0
 [INFO PPL-0005] Slots per section         200
 [INFO PPL-0008] Successfully assigned pins to sections.
-[INFO PPL-0012] I/O nets HPWL: 9534.38 um.
+[INFO PPL-0012] I/O nets HPWL: 1057.01 um.
 [INFO GPL-0001] ---- Initialize GPL Main Data Structures
 [INFO GPL-0002] DBU: 2000
 [INFO GPL-0003] SiteSize: (  0.190  1.400 ) um
@@ -44,12 +44,12 @@ Using 2 tracks default min distance between IO pins.
 [INFO GPL-0021] Large instances area:            0.000 um^2
 [INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement.
 [INFO GPL-0051] Source of initial instance position counters:
-	Odb location = 0	Core center = 81	Region center = 0
-[InitialPlace]  Iter: 1 conjugate gradient residual: 0.00000008 HPWL: 57583840
-[InitialPlace]  Iter: 2 conjugate gradient residual: 0.00000011 HPWL: 726067
-[InitialPlace]  Iter: 3 conjugate gradient residual: 0.00000010 HPWL: 722585
-[InitialPlace]  Iter: 4 conjugate gradient residual: 0.00000009 HPWL: 723827
-[InitialPlace]  Iter: 5 conjugate gradient residual: 0.00000008 HPWL: 725177
+	Odb location = 18	Core center = 63	Region center = 0
+[InitialPlace]  Iter: 1 conjugate gradient residual: 0.00000006 HPWL: 1722700
+[InitialPlace]  Iter: 2 conjugate gradient residual: 0.00000005 HPWL: 8121024
+[InitialPlace]  Iter: 3 conjugate gradient residual: 0.00000011 HPWL: 2164788
+[InitialPlace]  Iter: 4 conjugate gradient residual: 0.00000010 HPWL: 1701248
+[InitialPlace]  Iter: 5 conjugate gradient residual: 0.00000007 HPWL: 1688200
 [INFO DPL-0006] Core area: 999570.01 um^2, Instances area: 121.56 um^2, Utilization: 0.0%
 [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically.
 [INFO DPL-1101] Legalizing using diamond search.
@@ -64,12 +64,12 @@ Total Placement Failures:          0
 ---------------------------------------
 Placement Analysis
 ---------------------------------
-total displacement        677.8 u
-average displacement        8.4 u
-max displacement           11.0 u
-original HPWL              94.0 u
-legalized HPWL           1099.7 u
-delta HPWL                 1070 %
+total displacement        798.6 u
+average displacement        9.9 u
+max displacement           13.0 u
+original HPWL             573.2 u
+legalized HPWL           1628.1 u
+delta HPWL                  184 %
 
 [INFO CTS-0050] Root buffer is BUF_X1.
 [INFO CTS-0051] Sink buffer is BUF_X1.
@@ -88,14 +88,14 @@ delta HPWL                 1070 %
 [INFO CTS-0030]  Number of static layers: 1.
 [INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
 [INFO CTS-0021]  Distance between buffers: 7 units (100 um).
-[INFO CTS-0023]  Original sink region: [(979130, 1989230), (1007190, 1997975)].
-[INFO CTS-0024]  Normalized sink region: [(69.9379, 142.088), (71.9421, 142.713)].
-[INFO CTS-0025]     Width:  2.0043.
-[INFO CTS-0026]     Height: 0.6246.
+[INFO CTS-0023]  Original sink region: [(3230, 1230), (10890, 18025)].
+[INFO CTS-0024]  Normalized sink region: [(0.230714, 0.0878571), (0.777857, 1.2875)].
+[INFO CTS-0025]     Width:  0.5471.
+[INFO CTS-0026]     Height: 1.1996.
  Level 1
-    Direction: Horizontal
+    Direction: Vertical
     Sinks per sub-region: 5
-    Sub-region size: 1.0021 X 0.6246
+    Sub-region size: 0.5471 X 0.5998
 [INFO CTS-0034]     Segment length (rounded): 1.
 [INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
 [INFO CTS-0035]  Number of sinks covered: 9.
@@ -108,6 +108,6 @@ delta HPWL                 1070 %
 [INFO CTS-0098] Clock net "clk"
 [INFO CTS-0099]  Sinks 10
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 21.43 um
+[INFO CTS-0101]  Average sink wire length 506.70 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Dummy loads inserted 1