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Merge pull request #10298 from The-OpenROAD-Project-staging/resolve_spef_def
dbSta: SpefReader name-escape regression for DEF+SPEF flow + OpenSTA submodule bump
2 parents df15ee7 + ff0d6b1 commit d87cb90

7 files changed

Lines changed: 267 additions & 1 deletion

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‎src/dbSta/test/BUILD‎

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@@ -58,6 +58,7 @@ ALL_TESTS = [
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"sdc_get1",
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"sdc_names1",
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"sdc_names2",
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"spef_def_names",
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"sta1",
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"sta2",
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"sta3",
@@ -200,6 +201,10 @@ filegroup(
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"sdc_names1": [
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"hier1.def",
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],
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"spef_def_names": [
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"example1_slow.lib",
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"example1.lef",
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],
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"sta1": [
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"example1_slow.lib",
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"example1.def",

‎src/dbSta/test/CMakeLists.txt‎

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@@ -48,6 +48,7 @@ or_integration_tests(
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sdc_get1
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sdc_names1
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sdc_names2
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spef_def_names
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sta1
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sta2
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sta3

‎src/dbSta/test/spef_def_names.def‎

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VERSION 5.5 ;
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NAMESCASESENSITIVE ON ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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DESIGN top ;
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UNITS DISTANCE MICRONS 1000 ;
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DIEAREA ( 0 0 ) ( 1000 1000 ) ;
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# Names exercise three patterns:
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# - plain identifier (baseline) : b_plain, n_plain
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# - flat name with literal '/' (CTS-style) : cts/leaf_buf, cts/leaf_net
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# - flat name with literal '[]' (bus-bit) : bus[0], bus_n[0]
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COMPONENTS 6 ;
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- b_plain BUF_X1 ;
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- cts/leaf_buf BUF_X1 ;
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- bus[0] BUF_X1 ;
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- b_sink_a BUF_X1 ;
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- b_sink_b BUF_X1 ;
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- b_sink_c BUF_X1 ;
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END COMPONENTS
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PINS 2 ;
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- in + NET in + DIRECTION INPUT ;
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- out + NET out + DIRECTION OUTPUT ;
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END PINS
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NETS 7 ;
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- in ( PIN in ) ( b_plain A ) ( cts/leaf_buf A ) ( bus[0] A ) ;
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- n_plain ( b_plain Z ) ( b_sink_a A ) ;
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- cts/leaf_net ( cts/leaf_buf Z ) ( b_sink_b A ) ;
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- bus_n[0] ( bus[0] Z ) ( b_sink_c A ) ;
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- s_a ( b_sink_a Z ) ;
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- s_b ( b_sink_b Z ) ;
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- out ( b_sink_c Z ) ( PIN out ) ;
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END NETS
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END DESIGN

‎src/dbSta/test/spef_def_names.ok‎

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[INFO ODB-0227] LEF file: example1.lef, created 2 layers, 6 library cells
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[INFO ODB-0128] Design: top
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[INFO ODB-0130] Created 2 pins.
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[INFO ODB-0131] Created 6 components and 24 component-terminals.
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[INFO ODB-0133] Created 7 nets and 12 connections.
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[WARNING ORD-2056] The following 128 liberty cell(s) do not have LEF masters and will be marked as dont-use:
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AND2_X2
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AND2_X4
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AND3_X1
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AND3_X2
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AND3_X4
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AND4_X1
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AND4_X2
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AND4_X4
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ANTENNA_X1
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AOI211_X1
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AOI211_X2
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AOI211_X4
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AOI21_X1
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AOI21_X2
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AOI21_X4
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AOI221_X1
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AOI221_X2
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AOI221_X4
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AOI222_X1
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AOI222_X2
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AOI222_X4
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AOI22_X1
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AOI22_X2
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AOI22_X4
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BUF_X16
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BUF_X32
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BUF_X4
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BUF_X8
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CLKBUF_X1
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CLKBUF_X2
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CLKBUF_X3
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CLKGATETST_X1
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CLKGATETST_X2
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CLKGATETST_X4
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CLKGATETST_X8
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CLKGATE_X1
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CLKGATE_X2
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CLKGATE_X4
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CLKGATE_X8
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DFFRS_X1
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DFFRS_X2
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DFFR_X1
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DFFR_X2
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DFFS_X1
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DFFS_X2
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DFF_X2
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DLH_X1
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DLH_X2
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DLL_X1
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DLL_X2
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FA_X1
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FILLCELL_X1
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FILLCELL_X16
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FILLCELL_X2
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FILLCELL_X32
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FILLCELL_X4
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FILLCELL_X8
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HA_X1
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INV_X16
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INV_X2
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INV_X32
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INV_X4
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INV_X8
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LOGIC0_X1
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LOGIC1_X1
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MUX2_X1
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MUX2_X2
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NAND2_X1
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NAND2_X2
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NAND2_X4
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NAND3_X1
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NAND3_X2
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NAND3_X4
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NAND4_X1
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NAND4_X2
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NAND4_X4
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NOR2_X2
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NOR2_X4
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NOR3_X1
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NOR3_X2
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NOR3_X4
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NOR4_X1
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NOR4_X2
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NOR4_X4
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OAI211_X1
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OAI211_X2
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OAI211_X4
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OAI21_X1
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OAI21_X2
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OAI21_X4
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OAI221_X1
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OAI221_X2
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OAI221_X4
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OAI222_X1
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OAI222_X2
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OAI222_X4
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OAI22_X1
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OAI22_X2
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OAI22_X4
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OAI33_X1
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OR2_X1
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OR2_X2
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OR2_X4
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OR3_X1
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OR3_X2
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OR3_X4
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OR4_X1
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OR4_X2
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OR4_X4
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SDFFRS_X1
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SDFFRS_X2
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SDFFR_X1
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SDFFR_X2
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SDFFS_X1
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SDFFS_X2
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SDFF_X1
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SDFF_X2
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TBUF_X1
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TBUF_X16
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TBUF_X2
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TBUF_X4
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TBUF_X8
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TINV_X1
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TLAT_X1
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XNOR2_X1
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XNOR2_X2
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XOR2_X1
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XOR2_X2
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spef_def_names: read_spef done

‎src/dbSta/test/spef_def_names.spef‎

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*SPEF "IEEE 1481-1998"
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*DESIGN "top"
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*DATE "Mon Jan 1 00:00:00 2026"
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*VENDOR "synthetic"
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*PROGRAM "spef_def_names"
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*VERSION "1.0"
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*DESIGN_FLOW "MISSING_NETS"
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*DIVIDER /
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*DELIMITER :
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*BUS_DELIMITER [ ]
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*T_UNIT 1.0 PS
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*C_UNIT 1.0 PF
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*R_UNIT 1.0 OHM
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*L_UNIT 1.0 HENRY
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*PORTS
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in I
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out O
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*D_NET in 0.300
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*CONN
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*P in I
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*I b_plain:A I *L .003
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*I cts\/leaf_buf:A I *L .003
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*I bus\[0\]:A I *L .003
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*CAP
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1 in 0.10
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2 b_plain:A 0.05
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3 cts\/leaf_buf:A 0.05
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4 bus\[0\]:A 0.05
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*RES
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5 in b_plain:A 50
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6 in cts\/leaf_buf:A 50
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7 in bus\[0\]:A 50
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*END
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*D_NET n_plain 0.250
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*CONN
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*I b_plain:Z O
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*I b_sink_a:A I *L .003
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*CAP
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1 b_plain:Z 0.10
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2 b_sink_a:A 0.05
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*RES
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3 b_plain:Z b_sink_a:A 50
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*END
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*D_NET cts\/leaf_net 0.250
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*CONN
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*I cts\/leaf_buf:Z O
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*I b_sink_b:A I *L .003
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*CAP
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1 cts\/leaf_buf:Z 0.10
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2 b_sink_b:A 0.05
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*RES
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3 cts\/leaf_buf:Z b_sink_b:A 50
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*END
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*D_NET bus_n\[0\] 0.250
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*CONN
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*I bus\[0\]:Z O
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*I b_sink_c:A I *L .003
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*CAP
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1 bus\[0\]:Z 0.10
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2 b_sink_c:A 0.05
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*RES
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3 bus\[0\]:Z b_sink_c:A 50
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*END

‎src/dbSta/test/spef_def_names.tcl‎

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# Regression for SpefReader name-escape lookups when the netlist comes from
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# DEF rather than verilog. The DEF stores instance/net names verbatim with
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# literal '/' (post-CTS-style flat names) and '[]' (bus bits); the SPEF
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# follows the SPEF grammar and decorates those characters with backslash
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# escapes ('\/', '\[', '\]'). Without the SpefReader fallbacks, lookups for
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# the slash- and bracket-bearing names would all miss because:
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# * Network::findInstanceRelative splits at unescaped '/' -> hierarchy walk
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# finds no parent matching the pre-'/' segment, and
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# * dbNetwork's literal block_->find* expects the unescaped form actually
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# stored by the DEF reader.
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# Pass criterion: read_spef completes with no STA-1648/1650/1651 warnings.
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source "helpers.tcl"
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read_lef example1.lef
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read_liberty example1_slow.lib
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read_def spef_def_names.def
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read_spef spef_def_names.spef
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puts "spef_def_names: read_spef done"

‎src/sta‎

Submodule sta updated 38 files

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