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sta: add tests for sta -> db converters
Signed-off-by: Peter Gadfort <gadfort@zeroasic.com>
1 parent 6038a52 commit da853fb

6 files changed

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‎src/dbSta/test/BUILD‎

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@@ -64,6 +64,8 @@ ALL_TESTS = [
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"sta3",
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"sta4",
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"sta5",
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"sta_to_db1",
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"sta_to_db1_hier",
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"write_sdc1",
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"write_verilog1",
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"write_verilog2",
@@ -236,6 +238,16 @@ filegroup(
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"example1.def",
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"example1.lef",
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],
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"sta_to_db1": [
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"example1_slow.lib",
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"example1.def",
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"example1.lef",
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],
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"sta_to_db1_hier": [
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"example1_typ.lib",
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"example1.lef",
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"hier3.v",
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],
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"write_sdc1": [
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"hier1.sdc",
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"hier1.v",

‎src/dbSta/test/CMakeLists.txt‎

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@@ -54,6 +54,8 @@ or_integration_tests(
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sta3
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sta4
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sta5
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sta_to_db1
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sta_to_db1_hier
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write_sdc1
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write_verilog1
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write_verilog2

‎src/dbSta/test/sta_to_db1.ok‎

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[INFO ODB-0227] LEF file: example1.lef, created 2 layers, 6 library cells
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[INFO ODB-0128] Design: top
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[INFO ODB-0130] Created 6 pins.
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[INFO ODB-0131] Created 5 components and 24 component-terminals.
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[INFO ODB-0132] Created 2 special nets and 10 connections.
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[INFO ODB-0133] Created 10 nets and 14 connections.
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[WARNING ORD-2056] The following 128 liberty cell(s) do not have LEF masters and will be marked as dont-use:
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AND2_X2
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AND2_X4
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AND3_X1
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AND3_X2
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AND3_X4
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AND4_X1
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AND4_X2
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AND4_X4
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ANTENNA_X1
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AOI211_X1
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AOI211_X2
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AOI211_X4
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AOI21_X1
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AOI21_X2
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AOI21_X4
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AOI221_X1
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AOI221_X2
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AOI221_X4
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AOI222_X1
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AOI222_X2
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AOI222_X4
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AOI22_X1
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AOI22_X2
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AOI22_X4
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BUF_X16
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BUF_X32
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BUF_X4
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BUF_X8
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CLKBUF_X1
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CLKBUF_X2
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CLKBUF_X3
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CLKGATETST_X1
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CLKGATETST_X2
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CLKGATETST_X4
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CLKGATETST_X8
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CLKGATE_X1
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CLKGATE_X2
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CLKGATE_X4
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CLKGATE_X8
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DFFRS_X1
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DFFRS_X2
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DFFR_X1
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DFFR_X2
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DFFS_X1
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DFFS_X2
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DFF_X2
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DLH_X1
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DLH_X2
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DLL_X1
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DLL_X2
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FA_X1
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FILLCELL_X1
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FILLCELL_X16
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FILLCELL_X2
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FILLCELL_X32
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FILLCELL_X4
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FILLCELL_X8
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HA_X1
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INV_X16
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INV_X2
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INV_X32
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INV_X4
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INV_X8
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LOGIC0_X1
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LOGIC1_X1
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MUX2_X1
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MUX2_X2
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NAND2_X1
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NAND2_X2
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NAND2_X4
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NAND3_X1
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NAND3_X2
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NAND3_X4
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NAND4_X1
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NAND4_X2
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NAND4_X4
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NOR2_X2
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NOR2_X4
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NOR3_X1
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NOR3_X2
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NOR3_X4
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NOR4_X1
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NOR4_X2
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NOR4_X4
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OAI211_X1
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OAI211_X2
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OAI211_X4
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OAI21_X1
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OAI21_X2
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OAI21_X4
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OAI221_X1
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OAI221_X2
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OAI221_X4
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OAI222_X1
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OAI222_X2
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OAI222_X4
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OAI22_X1
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OAI22_X2
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OAI22_X4
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OAI33_X1
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OR2_X1
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OR2_X2
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OR2_X4
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OR3_X1
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OR3_X2
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OR3_X4
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OR4_X1
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OR4_X2
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OR4_X4
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SDFFRS_X1
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SDFFRS_X2
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SDFFR_X1
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SDFFR_X2
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SDFFS_X1
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SDFFS_X2
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SDFF_X1
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SDFF_X2
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TBUF_X1
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TBUF_X16
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TBUF_X2
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TBUF_X4
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TBUF_X8
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TINV_X1
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TLAT_X1
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XNOR2_X1
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XNOR2_X2
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XOR2_X1
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XOR2_X2
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# leaf instance r1
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sta_to_db_inst: r1
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sta_to_db_mod_inst: NULL
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# leaf pin r1/D
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sta_to_db_pin: r1/D
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sta_to_db_mod_pin: NULL
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sta_pin_to_port: D
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# top-level port clk1
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sta_to_db_port: clk1
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sta_to_db_mod_port: NULL
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# net r1q
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sta_to_db_net: r1q
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sta_to_db_mod_net: NULL
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# liberty cell BUF_X1
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sta_to_db_master: BUF_X1
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# liberty port BUF_X1/A
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sta_to_db_mterm: A

‎src/dbSta/test/sta_to_db1.tcl‎

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# Exercise the sta::sta_to_db_* SWIG bindings on a flat design.
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#
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# All instances/pins/nets/ports are leaves (no dbModInst / dbModNet /
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# dbModITerm / dbModBTerm exist), so:
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# * sta_to_db_inst, _pin, _port, _net resolve to the matching dbInst /
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# dbITerm / dbBTerm / dbNet.
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# * sta_to_db_mod_inst, _mod_pin, _mod_port, _mod_net all return NULL.
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source "helpers.tcl"
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read_lef example1.lef
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read_liberty example1_slow.lib
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read_def example1.def
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proc check { label obj } {
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if { $obj == "NULL" } {
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puts "$label: NULL"
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return
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}
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set name [$obj getName]
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if { [catch { set hier [$obj getHierarchicalName] }] } {
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puts "$label: $name"
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} else {
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puts "$label: $name (hier: $hier)"
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}
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}
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proc check_port { label port } {
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if { $port == "NULL" } {
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puts "$label: <no port>"
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} else {
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puts "$label: [get_property $port full_name]"
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}
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}
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# --- leaf instance ---
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puts "# leaf instance r1"
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set inst [get_cells r1]
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check " sta_to_db_inst" [sta::sta_to_db_inst $inst]
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check " sta_to_db_mod_inst" [sta::sta_to_db_mod_inst $inst]
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# --- leaf instance pin ---
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puts "# leaf pin r1/D"
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set pin [get_pin r1/D]
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check " sta_to_db_pin" [sta::sta_to_db_pin $pin]
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check " sta_to_db_mod_pin" [sta::sta_to_db_mod_pin $pin]
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check_port " sta_pin_to_port" [sta::sta_pin_to_port $pin]
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# --- top-level Port ---
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puts "# top-level port clk1"
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set port [lindex [get_ports clk1] 0]
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check " sta_to_db_port" [sta::sta_to_db_port $port]
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check " sta_to_db_mod_port" [sta::sta_to_db_mod_port $port]
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# --- a flat dbNet ---
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puts "# net r1q"
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set net [get_net r1q]
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check " sta_to_db_net" [sta::sta_to_db_net $net]
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check " sta_to_db_mod_net" [sta::sta_to_db_mod_net $net]
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# --- LibertyCell -> dbMaster, LibertyPort -> dbMTerm ---
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puts "# liberty cell BUF_X1"
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set lib_cell [get_property [get_cells u1] liberty_cell]
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check " sta_to_db_master" [sta::sta_to_db_master $lib_cell]
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puts "# liberty port BUF_X1/A"
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set lib_port [lindex [get_lib_pins NangateOpenCellLibrary_slow/BUF_X1/A] 0]
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check " sta_to_db_mterm" [sta::sta_to_db_mterm $lib_port]

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