Merge pull request #10437 from The-OpenROAD-Project-staging/or_merge_sta_0514_report_generic

Update OpenSTA 5/14 code comes with report path field generalization, needs OpenROAD updation for mbff orig_name

Author: maliberty

src/gpl/src/mbff.cpp

@@ -929,27 +929,26 @@ void MBFF::ModifyPinConnections(const std::vector<Flop>& flops,
       }
 
       // Store original FF→tray pin mapping as a property on the tray
-      // instance so timing reports can display the original pin name.
-      std::string tray_port;
+      // pin (iterm) so the report_path "orig_name" field can display the
+      // original pin name.
+      dbITerm* tray_iterm = nullptr;
       if (is_d && d_pin) {
-        tray_port = d_pin->name();
+        tray_iterm = tray_inst[tray_idx]->findITerm(d_pin->name().c_str());
       } else if (is_q) {
-        if (is_qn_inv && qn_pin) {
-          tray_port = qn_pin->name();
-        } else if (q_pin) {
-          tray_port = q_pin->name();
+        const sta::LibertyPort* tray_port = is_qn_inv ? qn_pin : q_pin;
+        if (tray_port) {
+          tray_iterm
+              = tray_inst[tray_idx]->findITerm(tray_port->name().c_str());
         }
       }
-      if (!tray_port.empty()) {
-        const std::string key = "orig_name_" + tray_port;
+      if (tray_iterm) {
         const std::string val = orig_inst_name + "/" + orig_port_name;
         odb::dbStringProperty* prop
-            = odb::dbStringProperty::find(tray_inst[tray_idx], key.c_str());
+            = odb::dbStringProperty::find(tray_iterm, kOrigNameProp);
         if (prop) {
           prop->setValue(val.c_str());
         } else {
-          odb::dbStringProperty::create(
-              tray_inst[tray_idx], key.c_str(), val.c_str());
+          odb::dbStringProperty::create(tray_iterm, kOrigNameProp, val.c_str());
         }
       }
     }

src/gpl/src/mbff.h

@@ -32,6 +32,8 @@ class Scene;
 
 namespace gpl {
 
+inline constexpr const char* kOrigNameProp = "orig_name";
+
 struct Point;
 struct Tray;
 struct Flop;

src/gpl/src/replace.cpp

@@ -10,6 +10,7 @@
 #include <utility>
 
 #include "AbstractGraphics.h"
+#include "db_sta/dbNetwork.hh"
 #include "db_sta/dbSta.hh"
 #include "graphicsNone.h"
 #include "initialPlace.h"
@@ -21,7 +22,10 @@
 #include "placerBase.h"
 #include "routeBase.h"
 #include "rsz/Resizer.hh"
+#include "sta/Graph.hh"
+#include "sta/Path.hh"
 #include "sta/StaMain.hh"
+#include "sta/StaState.hh"
 #include "timingBase.h"
 #include "utl/Logger.h"
 #include "utl/validation.h"
@@ -38,6 +42,40 @@ Replace::Replace(odb::dbDatabase* odb,
     : db_(odb), sta_(sta), rs_(resizer), fr_(router), log_(logger)
 {
   graphics_ = std::make_unique<GraphicsNone>();
+
+  // Register "orig_name" report_path field: original pin name before
+  // multi-bit clustering. Reads "orig_name" property off the path
+  // vertex's iterm. Registered at tool init so paths can be reported
+  // even when the design is loaded from an already-clustered .odb
+  // without re-running cluster_flops.
+  if (sta_->findReportPathField(kOrigNameProp) == nullptr) {
+    sta::dbNetwork* network = sta_->getDbNetwork();
+    sta_->makeReportPathField(
+        kOrigNameProp,
+        kOrigNameProp,
+        "Orig Name",
+        36,
+        true,
+        nullptr,
+        [network](const sta::Path* path,
+                  const sta::StaState* sta) -> std::string {
+          if (path == nullptr) {
+            return {};
+          }
+          const sta::Pin* pin = path->vertex(sta)->pin();
+          // staToDb requires all three out-params; only iterm is used.
+          odb::dbITerm* iterm = nullptr;
+          odb::dbBTerm* bterm = nullptr;
+          odb::dbModITerm* moditerm = nullptr;
+          network->staToDb(pin, iterm, bterm, moditerm);
+          if (iterm == nullptr) {
+            return {};
+          }
+          odb::dbStringProperty* prop
+              = odb::dbStringProperty::find(iterm, kOrigNameProp);
+          return prop ? prop->getValue() : std::string{};
+        });
+  }
 }
 
 Replace::~Replace() = default;

src/gpl/test/mbff_orig_name.def

@@ -5,18 +5,23 @@
 [INFO ODB-0227] LEF file: ./4BitTrayH4/asap7sc7p5t_DFFHQNV4X.lef, created 9 library cells
 [INFO ODB-0394] Duplicate site asap7sc7p5t_pg in asap7sc7p5t_DFFHQNH2V2X already seen in asap7sc7p5t_DFFHQNV2X
 [INFO ODB-0227] LEF file: ./4BitTrayH2W2/asap7sc7p5t_DFFHQNH2V2X.lef, created 9 library cells
-[INFO ODB-0128] Design: tray_test
-[INFO ODB-0130]     Created 9 pins.
-[INFO ODB-0131]     Created 4 components and 20 component-terminals.
-[INFO ODB-0133]     Created 9 nets and 12 connections.
+orig_name field registered at session init (pre-cluster_flops).
+[WARNING IFP-0028] Core area lower left (1.000, 1.000) snapped to (1.026, 1.080).
+[INFO IFP-0001] Added 29 rows of 147 site asap7sc7p5t.
+[INFO IFP-0100] Die BBox:  (  0.000  0.000 ) ( 10.000 10.000 ) um
+[INFO IFP-0101] Core BBox: (  1.026  1.080 ) (  8.964  8.910 ) um
+[INFO IFP-0102] Core area:                           62.155 um^2
+[INFO IFP-0103] Total instances area:                 1.166 um^2
+[INFO IFP-0104] Effective utilization:                0.019
+[INFO IFP-0105] Number of instances:                      4
 Alpha = 40.0, Beta = 1.0, #paths = 0, max size = -1
 Total ILP Cost: 112.643
 Total Timing Critical Path Displacement: 0.0
 Average slot-to-flop displacement: 1.730
 Final Objective Value: 112.643
 Sizes used
   4-bit: 1
-Startpoint: d3 (input port clocked by clk)
+Startpoint: d4 (input port clocked by clk)
 Endpoint: _tray_size4_7 (rising edge-triggered flip-flop clocked by clk)
 Path Group: clk
 Path Type: max
@@ -26,8 +31,8 @@ Path Type: max
    0.00    0.00   clock clk (rise edge)
    0.00    0.00   clock network delay (ideal)
    0.00    0.00 ^ input external delay
-   0.00    0.00 ^ d3 (in)
-   0.00    0.00 ^ _tray_size4_7/D1 (DFFHQNV4Xx1_ASAP7_75t_L) ff3/D
+   0.00    0.00 ^ d4 (in)
+   0.00    0.00 ^ _tray_size4_7/D0 (DFFHQNV4Xx1_ASAP7_75t_L) ff4/D
            0.00   data arrival time
 
 1000.00 1000.00   clock clk (rise edge)

src/gpl/test/mbff_orig_name.ok

@@ -14,7 +14,26 @@ read_lib ./4BitTrayH4/asap7sc7p5t_DFFHQNV4X_LVT_TT_nldm_FAKE.lib
 read_lef ./4BitTrayH2W2/asap7sc7p5t_DFFHQNH2V2X.lef
 read_lib ./4BitTrayH2W2/asap7sc7p5t_DFFHQNH2V2X_LVT_TT_nldm_FAKE.lib
 
-read_def ./$test_name.def
+read_verilog ./$test_name.v
+link_design tray_test
+
+# Verify the "orig_name" report field is registered at session init
+# (Replace ctor), not deferred until cluster_flops. Required so an
+# already-clustered .odb loaded in a fresh session can still report
+# the saved orig_name properties via report_checks.
+if { [sta::find_report_path_field_abrev orig_name] == "" } {
+  utl::error GPL 330 "orig_name report_path field not registered at session init."
+}
+puts "orig_name field registered at session init (pre-cluster_flops)."
+
+initialize_floorplan -die_area "0 0 10 10" \
+  -core_area "1 1 9 9" \
+  -site asap7sc7p5t
+
+place_inst -name ff1 -origin {6 6} -status PLACED
+place_inst -name ff2 -origin {4 6} -status PLACED
+place_inst -name ff3 -origin {4 4} -status PLACED
+place_inst -name ff4 -origin {6 4} -status PLACED
 
 create_clock -name clk -period 1000 [get_ports clk1]
 set_input_delay -clock clk 0 [get_ports {d1 d2 d3 d4}]
@@ -24,6 +43,8 @@ cluster_flops -tray_weight 40.0 \
   -max_split_size -1 \
   -num_paths 0
 
-# Report timing to verify original FF names appear in the path report.
-# After clustering the tray pin descriptions should show in the Orig Name column.
-report_checks -path_delay max -fields {orig_name} -through [get_pins _tray_size4_7/D1]
+# Report timing to verify original FF pin names appear in the path
+# report. After clustering the tray pin descriptions show the ffN/D
+# mapping in the Orig Name column.
+report_checks -path_delay max -fields {orig_name} \
+  -through [get_pins -of_objects [get_cells _tray_size4_*]]

src/gpl/test/mbff_orig_name.tcl

@@ -0,0 +1,16 @@
+module tray_test (clk1, d1, d2, d3, d4, o1, o2, o3, o4);
+  input  clk1;
+  input  d1;
+  input  d2;
+  input  d3;
+  input  d4;
+  output o1;
+  output o2;
+  output o3;
+  output o4;
+
+  DFFHQNx1_ASAP7_75t_L ff1 (.CLK(clk1), .D(d1), .QN(o1));
+  DFFHQNx1_ASAP7_75t_L ff2 (.CLK(clk1), .D(d2), .QN(o2));
+  DFFHQNx1_ASAP7_75t_L ff3 (.CLK(clk1), .D(d3), .QN(o3));
+  DFFHQNx1_ASAP7_75t_L ff4 (.CLK(clk1), .D(d4), .QN(o4));
+endmodule