Merge pull request #10646 from The-OpenROAD-Project-staging/secure-fix-cts-propagated-clock

cts: Preserve virtual clock latency

Author: maliberty

src/cts/src/TritonCTS.cpp

@@ -2574,6 +2574,10 @@ void TritonCTS::setAllClocksPropagated()
   for (sta::Mode* mode : openSta_->modes()) {
     sta::Sdc* sdc = mode->sdc();
     for (sta::Clock* clk : sdc->clocks()) {
+      // Virtual clocks model external timing and must keep their latency.
+      if (clk->isVirtual()) {
+        continue;
+      }
       openSta_->setPropagatedClock(clk, mode);
     }
   }

src/cts/test/BUILD

@@ -51,6 +51,7 @@ COMPULSORY_TESTS = [
     "sink_clustering_collision",
     "skip_nets",
     "twice",
+    "virtual_clock_latency",
 ]
 
 ALL_TESTS = COMPULSORY_TESTS
@@ -217,6 +218,9 @@ filegroup(
             "twice": [
                 "16sinks.def",
             ],
+            "virtual_clock_latency": [
+                "16sinks.def",
+            ],
         }.get(test_name, []),
     )
     for test_name in ALL_TESTS

src/cts/test/CMakeLists.txt

@@ -46,6 +46,7 @@ or_integration_tests(
     sink_clustering_collision
     skip_nets
     twice
+    virtual_clock_latency
 )
 
 add_executable(cts_unittest cts_unittest.cc)
@@ -69,4 +70,3 @@ gtest_discover_tests(cts_unittest
 )
 
 add_dependencies(build_and_test cts_unittest)
-

src/cts/test/virtual_clock_latency.ok

@@ -0,0 +1,44 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0128] Design: test_16_sinks
+[INFO ODB-0130]     Created 1 pins.
+[INFO ODB-0131]     Created 16 components and 96 component-terminals.
+[INFO ODB-0133]     Created 1 nets and 16 connections.
+[INFO CTS-0050] Root buffer is CLKBUF_X3.
+[INFO CTS-0051] Sink buffer is CLKBUF_X3.
+[INFO CTS-0052] The following clock buffers will be used for CTS:
+                    CLKBUF_X3
+[INFO CTS-0049] Characterization buffer is CLKBUF_X3.
+[INFO CTS-0007] Net "clk" found for clock "clk".
+[INFO CTS-0010]  Clock net "clk" has 16 sinks.
+[INFO CTS-0008] TritonCTS found 1 clock nets.
+[INFO CTS-0097] Characterization used 1 buffer(s) types.
+[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
+[INFO CTS-0027] Generating H-Tree topology for net clk.
+[INFO CTS-0028]  Total number of sinks: 16.
+[INFO CTS-0030]  Number of static layers: 0.
+[INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
+[INFO CTS-0023]  Original sink region: [(3730, 1730), (22730, 20730)].
+[INFO CTS-0024]  Normalized sink region: [(0.266429, 0.123571), (1.62357, 1.48071)].
+[INFO CTS-0025]     Width:  1.3571.
+[INFO CTS-0026]     Height: 1.3571.
+ Level 1
+    Direction: Vertical
+    Sinks per sub-region: 8
+    Sub-region size: 1.3571 X 0.6786
+[INFO CTS-0034]     Segment length (rounded): 1.
+[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
+[INFO CTS-0035]  Number of sinks covered: 16.
+[INFO CTS-0018]     Created 3 clock buffers.
+[INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
+[INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
+[INFO CTS-0015]     Created 3 clock nets.
+[INFO CTS-0016]     Fanout distribution for the current clock = 8:2..
+[INFO CTS-0017]     Max level of the clock tree: 1.
+[INFO CTS-0098] Clock net "clk"
+[INFO CTS-0099]  Sinks 16
+[INFO CTS-0100]  Leaf buffers 0
+[INFO CTS-0101]  Average sink wire length 18.87 um
+[INFO CTS-0102]  Path depth 2 - 2
+[INFO CTS-0207]  Dummy loads inserted 0
+vclk latency preserved: 1
+vclk propagated written: 0

src/cts/test/virtual_clock_latency.tcl

@@ -0,0 +1,35 @@
+source "helpers.tcl"
+read_lef Nangate45/Nangate45.lef
+read_liberty Nangate45/Nangate45_typ.lib
+read_def "16sinks.def"
+
+create_clock -period 5 clk
+create_clock -name vclk -period 5
+set_clock_latency 0.2 [get_clocks vclk]
+
+set_wire_rc -clock -layer metal3
+
+set_cts_config -wire_unit 20 \
+  -apply_ndr root_only \
+  -root_buf CLKBUF_X3 \
+  -buf_list CLKBUF_X3
+
+clock_tree_synthesis
+
+set sdc_file [make_result_file virtual_clock_latency.sdc]
+write_sdc -no_timestamp $sdc_file
+
+set stream [open $sdc_file r]
+set sdc_text [read $stream]
+close $stream
+
+set vclk_latency_found \
+  [regexp {set_clock_latency 0\.2000 \[get_clocks \{vclk\}\]} $sdc_text]
+set vclk_propagated_found \
+  [regexp {set_propagated_clock \[get_clocks \{vclk\}\]} $sdc_text]
+
+# vclk latency should be preserved
+puts "vclk latency preserved: $vclk_latency_found"
+
+# vclk cannot be propagated
+puts "vclk propagated written: $vclk_propagated_found"