dbSta: rename StalePrevPath test and derive verilog filename from gtest info

Tighten the test-name <-> verilog-file coupling so future stale-path
variants can just drop a new TestDbSta_<Name>.v alongside a new TEST_F
without touching the data list: use gtest's current_test_info() at
runtime to build the filename, matching the pattern already used in
src/rsz/test/cpp/TestInsertBuffer.cpp.

Test renamed StalePrevPathAfterUpdateTiming -> StalePrevPath (the
"AfterUpdateTiming" qualifier was redundant with the flow header).
Verilog renamed TestDbSta_StalePath.v -> TestDbSta_StalePrevPath.v to
match.

Signed-off-by: Minju Kim <mkim@precisioninno.com>

Author: minjukim55

src/dbSta/test/BUILD

@@ -292,7 +292,7 @@ cc_test(
         "Nangate45/Nangate45.lef",
         "Nangate45/Nangate45_typ.lib",
         "cpp/TestDbSta_0.v",
-        "cpp/TestDbSta_StalePath.v",
+        "cpp/TestDbSta_StalePrevPath.v",
     ],
     deps = [
         "//src/dbSta",

src/dbSta/test/cpp/TestDbSta.cc

@@ -104,7 +104,7 @@ TEST_F(TestDbSta, TestHierarchyConnectivity)
 
 // Regression for #10210 (stale Path* dereference in rsz).
 //
-// Topology (TestDbSta_StalePath.v):
+// Topology (TestDbSta_StalePrevPath.v):
 //   clk -> b1(BUF) -> inv1(INV) -> nd1(NAND2) -> out1
 //                                   nd1/A2 <- in2
 //
@@ -115,9 +115,12 @@ TEST_F(TestDbSta, TestHierarchyConnectivity)
 //   4. Assert the captured Path's prev slot has been recycled: pin()
 //      decodes to data that belongs to a different instance than nd1's
 //      real input.
-TEST_F(TestDbSta, StalePrevPathAfterUpdateTiming)
+TEST_F(TestDbSta, StalePrevPath)
 {
-  readVerilogAndSetup("TestDbSta_StalePath.v");
+  const auto* test_info = testing::UnitTest::GetInstance()->current_test_info();
+  const std::string test_name
+      = std::string(test_info->test_suite_name()) + "_" + test_info->name();
+  readVerilogAndSetup(test_name + ".v");
   sta_->updateTiming(true);
 
   Network* network = sta_->network();