@@ -197,11 +197,8 @@ bool SplitLoadMove::doMove(const Path* drvr_path,
197197 Vertex* load_vertex = fanout_slack.first ;
198198 Pin* load_pin = load_vertex->pin ();
199199
200- odb::dbITerm* load_iterm;
201- odb::dbBTerm* load_bterm;
202- odb::dbModITerm* load_moditerm;
203-
204- db_network_->staToDb (load_pin, load_iterm, load_bterm, load_moditerm);
200+ odb::dbITerm* load_iterm = nullptr ;
201+ load_iterm = db_network_->flatPin (load_pin);
205202
206203 // Leave ports connected to original net so verilog port names are
207204 // preserved.
@@ -235,10 +232,14 @@ bool SplitLoadMove::doMove(const Path* drvr_path,
235232 unique_connection_name.c_str ());
236233 }
237234 } else {
238- odb::dbITerm* iterm;
239- iterm = db_network_->flatPin (load_pin);
240- if (iterm && db_mod_load_net) {
241- iterm->connect (db_mod_load_net);
235+ if (load_iterm && db_mod_load_net) {
236+ // For hierarchical case, we simultaneously connect the
237+ // hierarchical net and the modnet to make sure they
238+ // get reassociated. (so all modnet pins refer to flat net).
239+ load_iterm->disconnect ();
240+ db_network_->connectPin (
241+ load_pin, (Net*) out_net, (Net*) db_mod_load_net);
242+ // iterm->connect(db_mod_load_net);
242243 }
243244 }
244245 }
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