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Merge pull request #10316 from gadfort/sta-debug
sta: expose the dbMod* in tcl
2 parents b0ea7ef + dd97687 commit f602970

8 files changed

Lines changed: 565 additions & 13 deletions

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‎src/dbSta/src/dbSta.i‎

Lines changed: 59 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -88,13 +88,21 @@ sta_to_db_inst(Instance *inst)
8888
{
8989
ord::OpenRoad *openroad = ord::getOpenRoad();
9090
sta::dbNetwork *db_network = openroad->getDbNetwork();
91-
odb::dbInst *db_inst;
92-
odb::dbModInst* mod_inst;
91+
odb::dbInst *db_inst = nullptr;
92+
odb::dbModInst* mod_inst = nullptr;
9393
db_network->staToDb(inst, db_inst, mod_inst);
94-
if (db_inst) {
95-
return db_inst;
96-
}
97-
return nullptr;
94+
return db_inst;
95+
}
96+
97+
odb::dbModInst *
98+
sta_to_db_mod_inst(Instance *inst)
99+
{
100+
ord::OpenRoad *openroad = ord::getOpenRoad();
101+
sta::dbNetwork *db_network = openroad->getDbNetwork();
102+
odb::dbInst *db_inst = nullptr;
103+
odb::dbModInst* mod_inst = nullptr;
104+
db_network->staToDb(inst, db_inst, mod_inst);
105+
return mod_inst;
98106
}
99107

100108
odb::dbMTerm *
@@ -111,25 +119,49 @@ sta_to_db_port(Port *port)
111119
ord::OpenRoad *openroad = ord::getOpenRoad();
112120
sta::dbNetwork *db_network = openroad->getDbNetwork();
113121
Pin *pin = db_network->findPin(db_network->topInstance(), port);
114-
odb::dbITerm *iterm;
115-
odb::dbBTerm *bterm;
116-
odb::dbModITerm *moditerm;
122+
odb::dbITerm *iterm = nullptr;
123+
odb::dbBTerm *bterm = nullptr;
124+
odb::dbModITerm *moditerm = nullptr;
117125
db_network->staToDb(pin, iterm, bterm, moditerm);
118126
return bterm;
119127
}
120128

129+
odb::dbModBTerm *
130+
sta_to_db_mod_port(Port *port)
131+
{
132+
ord::OpenRoad *openroad = ord::getOpenRoad();
133+
sta::dbNetwork *db_network = openroad->getDbNetwork();
134+
odb::dbBTerm *bterm = nullptr;
135+
odb::dbMTerm *mterm = nullptr;
136+
odb::dbModBTerm *modbterm = nullptr;
137+
db_network->staToDb(port, bterm, mterm, modbterm);
138+
return modbterm;
139+
}
140+
121141
odb::dbITerm *
122142
sta_to_db_pin(Pin *pin)
123143
{
124144
ord::OpenRoad *openroad = ord::getOpenRoad();
125145
sta::dbNetwork *db_network = openroad->getDbNetwork();
126-
odb::dbITerm *iterm;
127-
odb::dbBTerm *bterm;
128-
odb::dbModITerm *moditerm;
146+
odb::dbITerm *iterm = nullptr;
147+
odb::dbBTerm *bterm = nullptr;
148+
odb::dbModITerm *moditerm = nullptr;
129149
db_network->staToDb(pin, iterm, bterm, moditerm);
130150
return iterm;
131151
}
132152

153+
odb::dbModITerm *
154+
sta_to_db_mod_pin(Pin *pin)
155+
{
156+
ord::OpenRoad *openroad = ord::getOpenRoad();
157+
sta::dbNetwork *db_network = openroad->getDbNetwork();
158+
odb::dbITerm *iterm = nullptr;
159+
odb::dbBTerm *bterm = nullptr;
160+
odb::dbModITerm *moditerm = nullptr;
161+
db_network->staToDb(pin, iterm, bterm, moditerm);
162+
return moditerm;
163+
}
164+
133165
Port *
134166
sta_pin_to_port(Pin *pin)
135167
{
@@ -143,7 +175,21 @@ sta_to_db_net(Net *net)
143175
{
144176
ord::OpenRoad *openroad = ord::getOpenRoad();
145177
sta::dbNetwork *db_network = openroad->getDbNetwork();
146-
return db_network->staToDb(net);
178+
odb::dbNet *db_net = nullptr;
179+
odb::dbModNet *db_mod_net = nullptr;
180+
db_network->staToDb(net, db_net, db_mod_net);
181+
return db_net;
182+
}
183+
184+
odb::dbModNet *
185+
sta_to_db_mod_net(Net *net)
186+
{
187+
ord::OpenRoad *openroad = ord::getOpenRoad();
188+
sta::dbNetwork *db_network = openroad->getDbNetwork();
189+
odb::dbNet *db_net = nullptr;
190+
odb::dbModNet *db_mod_net = nullptr;
191+
db_network->staToDb(net, db_net, db_mod_net);
192+
return db_mod_net;
147193
}
148194

149195
odb::dbMaster *

‎src/dbSta/test/BUILD‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,8 @@ ALL_TESTS = [
6767
"sta3",
6868
"sta4",
6969
"sta5",
70+
"sta_to_db1",
71+
"sta_to_db1_hier",
7072
"write_sdc1",
7173
"write_verilog1",
7274
"write_verilog2",
@@ -249,6 +251,16 @@ filegroup(
249251
"example1.def",
250252
"example1.lef",
251253
],
254+
"sta_to_db1": [
255+
"example1_slow.lib",
256+
"example1.def",
257+
"example1.lef",
258+
],
259+
"sta_to_db1_hier": [
260+
"example1_typ.lib",
261+
"example1.lef",
262+
"hier3.v",
263+
],
252264
"write_sdc1": [
253265
"hier1.sdc",
254266
"hier1.v",

‎src/dbSta/test/CMakeLists.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,8 @@ or_integration_tests(
5757
sta3
5858
sta4
5959
sta5
60+
sta_to_db1
61+
sta_to_db1_hier
6062
write_sdc1
6163
write_verilog1
6264
write_verilog2

‎src/dbSta/test/sta_to_db1.ok‎

Lines changed: 152 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,152 @@
1+
[INFO ODB-0227] LEF file: example1.lef, created 2 layers, 6 library cells
2+
[INFO ODB-0128] Design: top
3+
[INFO ODB-0130] Created 6 pins.
4+
[INFO ODB-0131] Created 5 components and 24 component-terminals.
5+
[INFO ODB-0132] Created 2 special nets and 10 connections.
6+
[INFO ODB-0133] Created 10 nets and 14 connections.
7+
[WARNING ORD-2056] The following 128 liberty cell(s) do not have LEF masters and will be marked as dont-use:
8+
AND2_X2
9+
AND2_X4
10+
AND3_X1
11+
AND3_X2
12+
AND3_X4
13+
AND4_X1
14+
AND4_X2
15+
AND4_X4
16+
ANTENNA_X1
17+
AOI211_X1
18+
AOI211_X2
19+
AOI211_X4
20+
AOI21_X1
21+
AOI21_X2
22+
AOI21_X4
23+
AOI221_X1
24+
AOI221_X2
25+
AOI221_X4
26+
AOI222_X1
27+
AOI222_X2
28+
AOI222_X4
29+
AOI22_X1
30+
AOI22_X2
31+
AOI22_X4
32+
BUF_X16
33+
BUF_X32
34+
BUF_X4
35+
BUF_X8
36+
CLKBUF_X1
37+
CLKBUF_X2
38+
CLKBUF_X3
39+
CLKGATETST_X1
40+
CLKGATETST_X2
41+
CLKGATETST_X4
42+
CLKGATETST_X8
43+
CLKGATE_X1
44+
CLKGATE_X2
45+
CLKGATE_X4
46+
CLKGATE_X8
47+
DFFRS_X1
48+
DFFRS_X2
49+
DFFR_X1
50+
DFFR_X2
51+
DFFS_X1
52+
DFFS_X2
53+
DFF_X2
54+
DLH_X1
55+
DLH_X2
56+
DLL_X1
57+
DLL_X2
58+
FA_X1
59+
FILLCELL_X1
60+
FILLCELL_X16
61+
FILLCELL_X2
62+
FILLCELL_X32
63+
FILLCELL_X4
64+
FILLCELL_X8
65+
HA_X1
66+
INV_X16
67+
INV_X2
68+
INV_X32
69+
INV_X4
70+
INV_X8
71+
LOGIC0_X1
72+
LOGIC1_X1
73+
MUX2_X1
74+
MUX2_X2
75+
NAND2_X1
76+
NAND2_X2
77+
NAND2_X4
78+
NAND3_X1
79+
NAND3_X2
80+
NAND3_X4
81+
NAND4_X1
82+
NAND4_X2
83+
NAND4_X4
84+
NOR2_X2
85+
NOR2_X4
86+
NOR3_X1
87+
NOR3_X2
88+
NOR3_X4
89+
NOR4_X1
90+
NOR4_X2
91+
NOR4_X4
92+
OAI211_X1
93+
OAI211_X2
94+
OAI211_X4
95+
OAI21_X1
96+
OAI21_X2
97+
OAI21_X4
98+
OAI221_X1
99+
OAI221_X2
100+
OAI221_X4
101+
OAI222_X1
102+
OAI222_X2
103+
OAI222_X4
104+
OAI22_X1
105+
OAI22_X2
106+
OAI22_X4
107+
OAI33_X1
108+
OR2_X1
109+
OR2_X2
110+
OR2_X4
111+
OR3_X1
112+
OR3_X2
113+
OR3_X4
114+
OR4_X1
115+
OR4_X2
116+
OR4_X4
117+
SDFFRS_X1
118+
SDFFRS_X2
119+
SDFFR_X1
120+
SDFFR_X2
121+
SDFFS_X1
122+
SDFFS_X2
123+
SDFF_X1
124+
SDFF_X2
125+
TBUF_X1
126+
TBUF_X16
127+
TBUF_X2
128+
TBUF_X4
129+
TBUF_X8
130+
TINV_X1
131+
TLAT_X1
132+
XNOR2_X1
133+
XNOR2_X2
134+
XOR2_X1
135+
XOR2_X2
136+
# leaf instance r1
137+
sta_to_db_inst: r1
138+
sta_to_db_mod_inst: NULL
139+
# leaf pin r1/D
140+
sta_to_db_pin: r1/D
141+
sta_to_db_mod_pin: NULL
142+
sta_pin_to_port: D
143+
# top-level port clk1
144+
sta_to_db_port: clk1
145+
sta_to_db_mod_port: NULL
146+
# net r1q
147+
sta_to_db_net: r1q
148+
sta_to_db_mod_net: NULL
149+
# liberty cell BUF_X1
150+
sta_to_db_master: BUF_X1
151+
# liberty port BUF_X1/A
152+
sta_to_db_mterm: A

‎src/dbSta/test/sta_to_db1.tcl‎

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
# Exercise the sta::sta_to_db_* SWIG bindings on a flat design.
2+
#
3+
# All instances/pins/nets/ports are leaves (no dbModInst / dbModNet /
4+
# dbModITerm / dbModBTerm exist), so:
5+
# * sta_to_db_inst, _pin, _port, _net resolve to the matching dbInst /
6+
# dbITerm / dbBTerm / dbNet.
7+
# * sta_to_db_mod_inst, _mod_pin, _mod_port, _mod_net all return NULL.
8+
source "helpers.tcl"
9+
10+
read_lef example1.lef
11+
read_liberty example1_slow.lib
12+
read_def example1.def
13+
14+
proc check { label obj } {
15+
if { $obj == "NULL" } {
16+
puts "$label: NULL"
17+
return
18+
}
19+
set name [$obj getName]
20+
if { [catch { set hier [$obj getHierarchicalName] }] } {
21+
puts "$label: $name"
22+
} else {
23+
puts "$label: $name (hier: $hier)"
24+
}
25+
}
26+
27+
proc check_port { label port } {
28+
if { $port == "NULL" } {
29+
puts "$label: <no port>"
30+
} else {
31+
puts "$label: [get_property $port full_name]"
32+
}
33+
}
34+
35+
# --- leaf instance ---
36+
puts "# leaf instance r1"
37+
set inst [get_cells r1]
38+
check " sta_to_db_inst" [sta::sta_to_db_inst $inst]
39+
check " sta_to_db_mod_inst" [sta::sta_to_db_mod_inst $inst]
40+
41+
# --- leaf instance pin ---
42+
puts "# leaf pin r1/D"
43+
set pin [get_pin r1/D]
44+
check " sta_to_db_pin" [sta::sta_to_db_pin $pin]
45+
check " sta_to_db_mod_pin" [sta::sta_to_db_mod_pin $pin]
46+
check_port " sta_pin_to_port" [sta::sta_pin_to_port $pin]
47+
48+
# --- top-level Port ---
49+
puts "# top-level port clk1"
50+
set port [lindex [get_ports clk1] 0]
51+
check " sta_to_db_port" [sta::sta_to_db_port $port]
52+
check " sta_to_db_mod_port" [sta::sta_to_db_mod_port $port]
53+
54+
# --- a flat dbNet ---
55+
puts "# net r1q"
56+
set net [get_net r1q]
57+
check " sta_to_db_net" [sta::sta_to_db_net $net]
58+
check " sta_to_db_mod_net" [sta::sta_to_db_mod_net $net]
59+
60+
# --- LibertyCell -> dbMaster, LibertyPort -> dbMTerm ---
61+
puts "# liberty cell BUF_X1"
62+
set lib_cell [get_property [get_cells u1] liberty_cell]
63+
check " sta_to_db_master" [sta::sta_to_db_master $lib_cell]
64+
65+
puts "# liberty port BUF_X1/A"
66+
set lib_port [lindex [get_lib_pins NangateOpenCellLibrary_slow/BUF_X1/A] 0]
67+
check " sta_to_db_mterm" [sta::sta_to_db_mterm $lib_port]

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