Invalid SDF

[Lang-Ian]

I am attempting to run post layout simulation on an OpenROAD deisgn. So, here's a summary of what I did:

1. load the design into the GUI (read_liberty, read_db, read_verilog, read_sdc, read_spef);
2. Run report_checks - timing looks good;

Now export a verilog netlist and an sdf file (to be sure of consistent files):
3) write_verilog netlist.v
4) write_sdf -corner fast spi_register_block.fast.sdf

5. Load the simulation (which instantiates the exported netlist.v)
   Annotate from the test bench:
6. $sdf_annotate("spi_register_block.fast.sdf", path to netlist.v, , , "MAXIMUM");

And here's an excerpt of what I see:

• Hundreds of warnings like this: Bad $setuphold constraints: -181 ps and 178 ps. Limit sum must be greater than 0. Negative limit(s) set to zero.

• A large number of errors like this one: # ** Error (suppressible): (vsim-SDF-3262) spi_register_block.fast.sdf(26097): Failed to find matching specify timing constraint. [FD2D4(fast):../../../../../../../firmware/sensors/xxxx/yyyy/RTL/zzzz.v(2855)]

So it seems that the sdf is invalid (impossible setup and hold times) and it also doesn't perfectly match the netlist. I've been pretty careful to eliminate user error. So what's going on? Anybody any idea where to look? Do I have library problems?

[maliberty]

Can you provide a test case for the SDF generation? Its pretty hard to guess. Have you looked at the paths to such an endpoint to see if they look reasonable?

[Lang-Ian]

Thanks for your reply. I've managed to get the SDF to annotate by removing certain things from it:

For example, I have a timing check like this:

(TIMINGCHECK
(WIDTH (posedge RN) (0.253::0.253))
(REMOVAL (posedge RN) (posedge CK) (0.864::0.864))
(RECOVERY (posedge RN) (posedge CK) (-0.861::-0.861))
(SETUP (posedge D) (posedge CK) (-0.181::-0.177))
(SETUP (negedge D) (posedge CK) (-0.433::-0.428))
(HOLD (posedge D) (posedge CK) (0.179::0.177))
(HOLD (negedge D) (posedge CK) (0.366::0.364))
(WIDTH (posedge CK) (0.137::0.137))
(WIDTH (negedge CK) (0.161::0.161))
)

But, in the verilog description for the gate in question, there is no $removal specified.

Then, for some reason, I have this timing check:

(TIMINGCHECK
(WIDTH (posedge RN) (0.253::0.253))

But the library has the other edge:

$width(negedge RN, tminpwl$RN, 0, NOTIFIER);

And finally, most of my setup/hold checks seem to be invalid, like this one:

(TIMINGCHECK
(WIDTH (posedge RN) (0.253::0.253))
(RECOVERY (posedge RN) (posedge CK) (-0.861::-0.861))
(SETUP (posedge D) (posedge CK) (-0.181::-0.177))
(SETUP (negedge D) (posedge CK) (-0.433::-0.428))
(HOLD (posedge D) (posedge CK) (0.179::0.177))
(HOLD (negedge D) (posedge CK) (0.366::0.364))
(WIDTH (posedge CK) (0.137::0.137))
(WIDTH (negedge CK) (0.161::0.161))

So the sum of hold time and setup time is negative. In other words the signal can arrive after the point that it can be removed! It looks to me like the setup times should be positive, not negative. How or why does OpenROAD generate an SDF like that?

And finally, for a D flip flop, why is there a setup and hold for both edges of the clock?

Any thoughts please?