diff --git a/MODULE.bazel b/MODULE.bazel
index c7d8a6cf39d..40d0c597897 100644
--- a/MODULE.bazel
+++ b/MODULE.bazel
@@ -97,17 +97,6 @@ bazel_dep(name = "buildifier_prebuilt", version = "8.5.1.2", dev_dependency = Tr
 bazel_dep(name = "googletest", version = "1.17.0.bcr.2", dev_dependency = True)
 bazel_dep(name = "rules_verilator", version = "0.1.0", dev_dependency = True)
 bazel_dep(name = "verilator", version = "5.036.bcr.3", dev_dependency = True)
-
-# Used by chisel_binary from @bazel-orfs in test/orfs/mock-array
-bazel_dep(name = "rules_jvm_external", version = "6.4", dev_dependency = True)
-bazel_dep(name = "rules_chisel", version = "0.2.0", dev_dependency = True)
-single_version_override(
-    module_name = "rules_chisel",
-    patch_strip = 1,
-    patches = ["//:rules-chisel-dev-dep.patch"],
-)
-
-bazel_dep(name = "rules_scala", version = "7.1.5", dev_dependency = True)
 bazel_dep(name = "bazel-orfs", dev_dependency = True)
 bazel_dep(name = "bazel-orfs-verilog", dev_dependency = True)
 
@@ -194,69 +183,6 @@ orfs.default(
 )
 use_repo(orfs, "docker_orfs")
 
-SCALA_VERSION = "2.13.17"
-
-CHISEL_VERSION = "7.2.0"
-
-FIRTOOL_RESOLVER_VERSION = "2.0.1"
-
-scala_config = use_extension(
-    "@rules_scala//scala/extensions:config.bzl",
-    "scala_config",
-    dev_dependency = True,
-)
-scala_config.settings(
-    scala_version = SCALA_VERSION,
-)
-use_repo(scala_config, "rules_scala_config")
-
-scala_deps = use_extension(
-    "@rules_scala//scala/extensions:deps.bzl",
-    "scala_deps",
-    dev_dependency = True,
-)
-scala_deps.settings(
-    fetch_sources = True,
-)
-scala_deps.scala()
-
-chisel = use_extension("@rules_chisel//chisel:extensions.bzl", "chisel", dev_dependency = True)
-chisel.toolchain(
-    chisel_version = CHISEL_VERSION,
-    firtool_resolver_version = FIRTOOL_RESOLVER_VERSION,
-    scala_version = SCALA_VERSION,
-)
-use_repo(chisel, "chisel_maven")
-
-maven = use_extension("@rules_jvm_external//:extensions.bzl", "maven", dev_dependency = True)
-maven.install(
-    name = "maven",
-    artifacts = [
-    ],
-    # Update by running: bazelisk run @maven//:pin
-    lock_file = "//bazel:maven_install.json",
-    repositories = [
-        "https://repo1.maven.org/maven2",
-        "https://s01.oss.sonatype.org/content/repositories/releases",
-        "https://s01.oss.sonatype.org/content/repositories/snapshots",
-    ],
-)
-use_repo(maven, "maven")
-
-# --- External archives ---
-
-http_archive = use_repo_rule("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive")
-
-http_archive(
-    name = "circt",
-    build_file_content = """
-exports_files(glob(["bin/*"]), visibility = ["//visibility:public"])
-""",
-    sha256 = "b1b57d1b76ceba2bb37229dab53839d5db6d61394149708c71f6265565991ce6",
-    strip_prefix = "firtool-1.108.0",
-    url = "https://github.com/llvm/circt/releases/download/firtool-1.108.0/firrtl-bin-linux-x64.tar.gz",
-)
-
 # --- Overrides ---
 
 single_version_override(
diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock
index b1487ae82b1..92ae7c6211c 100644
--- a/MODULE.bazel.lock
+++ b/MODULE.bazel.lock
@@ -82,7 +82,6 @@
     "https://bcr.bazel.build/modules/bazel_skylib/1.4.1/MODULE.bazel": "a0dcb779424be33100dcae821e9e27e4f2901d9dfd5333efe5ac6a8d7ab75e1d",
     "https://bcr.bazel.build/modules/bazel_skylib/1.4.2/MODULE.bazel": "3bd40978e7a1fac911d5989e6b09d8f64921865a45822d8b09e815eaa726a651",
     "https://bcr.bazel.build/modules/bazel_skylib/1.5.0/MODULE.bazel": "32880f5e2945ce6a03d1fbd588e9198c0a959bb42297b2cfaf1685b7bc32e138",
-    "https://bcr.bazel.build/modules/bazel_skylib/1.6.0/MODULE.bazel": "f84162c41b86658c8a054584495594a94eae476555d07cc1d17507150e69f706",
     "https://bcr.bazel.build/modules/bazel_skylib/1.6.1/MODULE.bazel": "8fdee2dbaace6c252131c00e1de4b165dc65af02ea278476187765e1a617b917",
     "https://bcr.bazel.build/modules/bazel_skylib/1.7.0/MODULE.bazel": "0db596f4563de7938de764cc8deeabec291f55e8ec15299718b93c4423e9796d",
     "https://bcr.bazel.build/modules/bazel_skylib/1.7.1/MODULE.bazel": "3120d80c5861aa616222ec015332e5f8d3171e062e3e804a2a0253e1be26e59b",
@@ -90,8 +89,6 @@
     "https://bcr.bazel.build/modules/bazel_skylib/1.8.2/MODULE.bazel": "69ad6927098316848b34a9142bcc975e018ba27f08c4ff403f50c1b6e646ca67",
     "https://bcr.bazel.build/modules/bazel_skylib/1.9.0/MODULE.bazel": "72997b29dfd95c3fa0d0c48322d05590418edef451f8db8db5509c57875fb4b7",
     "https://bcr.bazel.build/modules/bazel_skylib/1.9.0/source.json": "7ad77c1e8c1b84222d9b3f3cae016a76639435744c19330b0b37c0a3c9da7dc0",
-    "https://bcr.bazel.build/modules/bazel_worker_api/0.0.6/MODULE.bazel": "fd1f9432ca04c947e91b500df69ce7c5b6dbfe1bc45ab1820338205dae3383a6",
-    "https://bcr.bazel.build/modules/bazel_worker_api/0.0.6/source.json": "5d68545f224904745a3cabd35aea6bc2b6cc5a78b7f49f3f69660eab2eeeb273",
     "https://bcr.bazel.build/modules/bliss/0.73/MODULE.bazel": "26b5476884b67df20a8b87ab2806657123b439e978da76f484427a15fb552b26",
     "https://bcr.bazel.build/modules/bliss/0.73/source.json": "5cb395710670662321f492fc3d4fce3551e3d5708682e4f2320bacaadf6e5e36",
     "https://bcr.bazel.build/modules/boost.algorithm/1.87.0/MODULE.bazel": "d1c8f1466cc1a04a16eebeefe0f54a9508cc9f1a3c21d65d806acbc36593e204",
@@ -501,8 +498,6 @@
     "https://bcr.bazel.build/modules/protobuf/27.0-rc2/MODULE.bazel": "b2b0dbafd57b6bec0ca9b251da02e628c357dab53a097570aa7d79d020f107cf",
     "https://bcr.bazel.build/modules/protobuf/27.0/MODULE.bazel": "7873b60be88844a0a1d8f80b9d5d20cfbd8495a689b8763e76c6372998d3f64c",
     "https://bcr.bazel.build/modules/protobuf/27.1/MODULE.bazel": "703a7b614728bb06647f965264967a8ef1c39e09e8f167b3ca0bb1fd80449c0d",
-    "https://bcr.bazel.build/modules/protobuf/27.2/MODULE.bazel": "32450b50673882e4c8c3d10a83f3bc82161b213ed2f80d17e38bece8f165c295",
-    "https://bcr.bazel.build/modules/protobuf/28.2/MODULE.bazel": "c0c8e51757df486d0314fa290e174d707bad4a6c2aa5ccb08a4b4abd76a23e90",
     "https://bcr.bazel.build/modules/protobuf/29.0-rc2/MODULE.bazel": "6241d35983510143049943fc0d57937937122baf1b287862f9dc8590fc4c37df",
     "https://bcr.bazel.build/modules/protobuf/29.0-rc3/MODULE.bazel": "33c2dfa286578573afc55a7acaea3cada4122b9631007c594bf0729f41c8de92",
     "https://bcr.bazel.build/modules/protobuf/29.0/MODULE.bazel": "319dc8bf4c679ff87e71b1ccfb5a6e90a6dbc4693501d471f48662ac46d04e4e",
@@ -580,8 +575,6 @@
     "https://bcr.bazel.build/modules/rules_cc/0.2.9/MODULE.bazel": "34263f1dca62ea664265438cef714d7db124c03e1ed55ebb4f1dc860164308d1",
     "https://bcr.bazel.build/modules/rules_cc_autoconf/0.7.15/MODULE.bazel": "0897d104c122e89a9a4e320b4f5b2c6fdded368052bc3e6c3d1f0728b4034187",
     "https://bcr.bazel.build/modules/rules_cc_autoconf/0.7.15/source.json": "641909c1438ce753c9ee69b4779eaa307ce334b1602cfba5ac6b9f66c26a37c7",
-    "https://bcr.bazel.build/modules/rules_chisel/0.2.0/MODULE.bazel": "25e67caac0df9d467c1867b46b5c2c45afd7a7ab05a8e7abb87cc1c758c37528",
-    "https://bcr.bazel.build/modules/rules_chisel/0.2.0/source.json": "e70a157e17ff14c1410a97ee1365e9abe00a7dd787830a237e1b612bcbc9a0f2",
     "https://bcr.bazel.build/modules/rules_flex/0.3.1/MODULE.bazel": "5aea738f59e47769d219f972fc8426c53693c262895787efafa71fe9795bd7e3",
     "https://bcr.bazel.build/modules/rules_flex/0.4/MODULE.bazel": "543edf994d2c044f3d723374e50eaa739ed7ee9d82b8185adb8413bce269dcf3",
     "https://bcr.bazel.build/modules/rules_flex/0.4/source.json": "98bc56c2139b6ed6387dbabd06f625e82500bed8ba1689a5f4f3c9e8c3289f82",
@@ -610,12 +603,10 @@
     "https://bcr.bazel.build/modules/rules_java/6.5.2/MODULE.bazel": "1d440d262d0e08453fa0c4d8f699ba81609ed0e9a9a0f02cd10b3e7942e61e31",
     "https://bcr.bazel.build/modules/rules_java/7.1.0/MODULE.bazel": "30d9135a2b6561c761bd67bd4990da591e6bdc128790ce3e7afd6a3558b2fb64",
     "https://bcr.bazel.build/modules/rules_java/7.10.0/MODULE.bazel": "530c3beb3067e870561739f1144329a21c851ff771cd752a49e06e3dc9c2e71a",
-    "https://bcr.bazel.build/modules/rules_java/7.11.1/MODULE.bazel": "b4782e019dd0b0151bd49fd8929136fd4441f527eb208fbd991b77e480b7236e",
     "https://bcr.bazel.build/modules/rules_java/7.12.2/MODULE.bazel": "579c505165ee757a4280ef83cda0150eea193eed3bef50b1004ba88b99da6de6",
     "https://bcr.bazel.build/modules/rules_java/7.2.0/MODULE.bazel": "06c0334c9be61e6cef2c8c84a7800cef502063269a5af25ceb100b192453d4ab",
     "https://bcr.bazel.build/modules/rules_java/7.3.2/MODULE.bazel": "50dece891cfdf1741ea230d001aa9c14398062f2b7c066470accace78e412bc2",
     "https://bcr.bazel.build/modules/rules_java/7.4.0/MODULE.bazel": "a592852f8a3dd539e82ee6542013bf2cadfc4c6946be8941e189d224500a8934",
-    "https://bcr.bazel.build/modules/rules_java/7.6.0/MODULE.bazel": "14cd36d05b60aa53c345b5b436c1c4a1f1dec58e82e480ffb9657038e323d330",
     "https://bcr.bazel.build/modules/rules_java/7.6.1/MODULE.bazel": "2f14b7e8a1aa2f67ae92bc69d1ec0fa8d9f827c4e17ff5e5f02e91caa3b2d0fe",
     "https://bcr.bazel.build/modules/rules_java/8.11.0/MODULE.bazel": "c3d280bc5ff1038dcb3bacb95d3f6b83da8dd27bba57820ec89ea4085da767ad",
     "https://bcr.bazel.build/modules/rules_java/8.14.0/MODULE.bazel": "717717ed40cc69994596a45aec6ea78135ea434b8402fb91b009b9151dd65615",
@@ -630,7 +621,6 @@
     "https://bcr.bazel.build/modules/rules_jvm_external/6.0/MODULE.bazel": "37c93a5a78d32e895d52f86a8d0416176e915daabd029ccb5594db422e87c495",
     "https://bcr.bazel.build/modules/rules_jvm_external/6.1/MODULE.bazel": "75b5fec090dbd46cf9b7d8ea08cf84a0472d92ba3585b476f44c326eda8059c4",
     "https://bcr.bazel.build/modules/rules_jvm_external/6.3/MODULE.bazel": "c998e060b85f71e00de5ec552019347c8bca255062c990ac02d051bb80a38df0",
-    "https://bcr.bazel.build/modules/rules_jvm_external/6.4/MODULE.bazel": "e859f460f0fcebbee0af2ac65a38c952eedb60612956395ba414fdf78babae2f",
     "https://bcr.bazel.build/modules/rules_jvm_external/6.7/MODULE.bazel": "e717beabc4d091ecb2c803c2d341b88590e9116b8bf7947915eeb33aab4f96dd",
     "https://bcr.bazel.build/modules/rules_jvm_external/6.7/source.json": "5426f412d0a7fc6b611643376c7e4a82dec991491b9ce5cb1cfdd25fe2e92be4",
     "https://bcr.bazel.build/modules/rules_kotlin/1.9.0/MODULE.bazel": "ef85697305025e5a61f395d4eaede272a5393cee479ace6686dba707de804d59",
@@ -684,10 +674,7 @@
     "https://bcr.bazel.build/modules/rules_python/1.7.0/MODULE.bazel": "d01f995ecd137abf30238ad9ce97f8fc3ac57289c8b24bd0bf53324d937a14f8",
     "https://bcr.bazel.build/modules/rules_python/1.8.5/MODULE.bazel": "28b2d79ed8368d7d45b34bacc220e3c0b99cbcd9392641961b849e4c3f55dd30",
     "https://bcr.bazel.build/modules/rules_python/1.8.5/source.json": "e261b03c8804f2582c9536013f987e1ea105a2b38c238aa2ac8f98fc34c8b18a",
-    "https://bcr.bazel.build/modules/rules_rust/0.45.1/MODULE.bazel": "a69d0db3a958fab2c6520961e1b2287afcc8b36690fd31bbc4f6f7391397150d",
     "https://bcr.bazel.build/modules/rules_rust/0.51.0/MODULE.bazel": "2b6d1617ac8503bfdcc0e4520c20539d4bba3a691100bee01afe193ceb0310f9",
-    "https://bcr.bazel.build/modules/rules_scala/7.1.5/MODULE.bazel": "72cd1d0ac56c3489b16c90857ac8938903402fc438a49168238ac58068f00741",
-    "https://bcr.bazel.build/modules/rules_scala/7.1.5/source.json": "cd45f7bf50c69e7c2f621ce2a1b199797502ebee994b181818169683e912c651",
     "https://bcr.bazel.build/modules/rules_shell/0.2.0/MODULE.bazel": "fda8a652ab3c7d8fee214de05e7a9916d8b28082234e8d2c0094505c5268ed3c",
     "https://bcr.bazel.build/modules/rules_shell/0.3.0/MODULE.bazel": "de4402cd12f4cc8fda2354fce179fdb068c0b9ca1ec2d2b17b3e21b24c1a937b",
     "https://bcr.bazel.build/modules/rules_shell/0.4.1/MODULE.bazel": "00e501db01bbf4e3e1dd1595959092c2fadf2087b2852d3f553b5370f5633592",
@@ -1520,185 +1507,6 @@
         "recordedRepoMappingEntries": []
       }
     },
-    "@@rules_chisel+//chisel:extensions.bzl%chisel": {
-      "general": {
-        "bzlTransitiveDigest": "+blXF/PncCsQI125MAJu2KliBdUnXm79a2ColXabdk0=",
-        "usagesDigest": "DGt57fukJ5xzo6u+WB4sIyT7lNznTva+pyfekI7/lxg=",
-        "recordedFileInputs": {},
-        "recordedDirentsInputs": {},
-        "envVariables": {},
-        "generatedRepoSpecs": {
-          "chisel_maven_internal": {
-            "repoRuleId": "@@rules_jvm_external+//private/rules:coursier.bzl%coursier_fetch",
-            "attributes": {
-              "pinned_repo_name": "",
-              "repositories": [
-                "{ \"repo_url\": \"https://repo1.maven.org/maven2\" }",
-                "{ \"repo_url\": \"https://s01.oss.sonatype.org/content/repositories/releases\" }"
-              ],
-              "artifacts": [
-                "{ \"group\": \"org.chipsalliance\", \"artifact\": \"chisel_2.13\", \"version\": \"7.2.0\" }",
-                "{ \"group\": \"org.chipsalliance\", \"artifact\": \"chisel-plugin_2.13.17\", \"version\": \"7.2.0\" }",
-                "{ \"group\": \"org.chipsalliance\", \"artifact\": \"firtool-resolver_2.13\", \"version\": \"2.0.1\" }",
-                "{ \"group\": \"org.scalatest\", \"artifact\": \"scalatest_2.13\", \"version\": \"3.2.19\" }"
-              ],
-              "boms": [],
-              "fail_on_missing_checksum": true,
-              "fetch_sources": true,
-              "fetch_javadoc": false,
-              "excluded_artifacts": [],
-              "generate_compat_repositories": false,
-              "version_conflict_policy": "default",
-              "override_targets": {},
-              "strict_visibility": false,
-              "strict_visibility_value": [
-                "@@//visibility:private"
-              ],
-              "resolve_timeout": 600,
-              "use_credentials_from_home_netrc_file": false,
-              "use_starlark_android_rules": false,
-              "aar_import_bzl_label": "@build_bazel_rules_android//android:rules.bzl",
-              "duplicate_version_warning": "warn",
-              "ignore_empty_files": false,
-              "additional_coursier_options": []
-            }
-          },
-          "chisel_maven": {
-            "repoRuleId": "@@rules_chisel+//chisel:extensions.bzl%_chisel_alias_repo",
-            "attributes": {
-              "deps_repo_name": "chisel_maven_internal",
-              "pin_repo_name": "chisel_maven_internal",
-              "scala_version": "2.13.17"
-            }
-          }
-        },
-        "moduleExtensionMetadata": {
-          "explicitRootModuleDirectDeps": [],
-          "explicitRootModuleDirectDevDeps": [
-            "chisel_maven"
-          ],
-          "useAllRepos": "NO",
-          "reproducible": false
-        },
-        "recordedRepoMappingEntries": [
-          [
-            "bazel_features+",
-            "bazel_features_globals",
-            "bazel_features++version_extension+bazel_features_globals"
-          ],
-          [
-            "bazel_features+",
-            "bazel_features_version",
-            "bazel_features++version_extension+bazel_features_version"
-          ],
-          [
-            "protobuf+",
-            "proto_bazel_features",
-            "bazel_features+"
-          ],
-          [
-            "protobuf+",
-            "rules_java",
-            "rules_java+"
-          ],
-          [
-            "rules_cc+",
-            "bazel_skylib",
-            "bazel_skylib+"
-          ],
-          [
-            "rules_cc+",
-            "bazel_tools",
-            "bazel_tools"
-          ],
-          [
-            "rules_cc+",
-            "cc_compatibility_proxy",
-            "rules_cc++compatibility_proxy+cc_compatibility_proxy"
-          ],
-          [
-            "rules_cc+",
-            "platforms",
-            "platforms"
-          ],
-          [
-            "rules_cc+",
-            "rules_cc",
-            "rules_cc+"
-          ],
-          [
-            "rules_cc++compatibility_proxy+cc_compatibility_proxy",
-            "rules_cc",
-            "rules_cc+"
-          ],
-          [
-            "rules_chisel+",
-            "rules_jvm_external",
-            "rules_jvm_external+"
-          ],
-          [
-            "rules_java+",
-            "bazel_features",
-            "bazel_features+"
-          ],
-          [
-            "rules_java+",
-            "bazel_skylib",
-            "bazel_skylib+"
-          ],
-          [
-            "rules_java+",
-            "bazel_tools",
-            "bazel_tools"
-          ],
-          [
-            "rules_java+",
-            "com_google_protobuf",
-            "protobuf+"
-          ],
-          [
-            "rules_java+",
-            "compatibility_proxy",
-            "rules_java++compatibility_proxy+compatibility_proxy"
-          ],
-          [
-            "rules_java+",
-            "rules_cc",
-            "rules_cc+"
-          ],
-          [
-            "rules_java++compatibility_proxy+compatibility_proxy",
-            "rules_java",
-            "rules_java+"
-          ],
-          [
-            "rules_jvm_external+",
-            "bazel_features",
-            "bazel_features+"
-          ],
-          [
-            "rules_jvm_external+",
-            "bazel_tools",
-            "bazel_tools"
-          ],
-          [
-            "rules_jvm_external+",
-            "rules_java",
-            "rules_java+"
-          ],
-          [
-            "rules_jvm_external+",
-            "rules_license",
-            "rules_license+"
-          ],
-          [
-            "rules_license+",
-            "rules_license",
-            "rules_license+"
-          ]
-        ]
-      }
-    },
     "@@rules_flex+//flex/internal:default_toolchain_ext.bzl%default_toolchain_ext": {
       "general": {
         "bzlTransitiveDigest": "IyvJbFvAYvjVrhYqrB8CJ8qfee94/AdZQhknVQYlFb8=",
diff --git a/bazel/maven_install.json b/bazel/maven_install.json
deleted file mode 100644
index ba6077e1332..00000000000
--- a/bazel/maven_install.json
+++ /dev/null
@@ -1,2077 +0,0 @@
-{
-  "__AUTOGENERATED_FILE_DO_NOT_MODIFY_THIS_FILE_MANUALLY": "THERE_IS_NO_DATA_ONLY_ZUUL",
-  "__INPUT_ARTIFACTS_HASH": 1590498176,
-  "__RESOLVED_ARTIFACTS_HASH": -1543679001,
-  "conflict_resolution": {
-    "com.google.errorprone:error_prone_annotations:2.5.1": "com.google.errorprone:error_prone_annotations:2.18.0",
-    "com.lihaoyi:os-lib_2.13:0.10.0": "com.lihaoyi:os-lib_2.13:0.10.7",
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-      "org.junit.jupiter:junit-jupiter-api",
-      "org.junit.jupiter:junit-jupiter-engine",
-      "org.junit.jupiter:junit-jupiter-params",
-      "org.junit.platform:junit-platform-commons",
-      "org.junit.platform:junit-platform-engine",
-      "org.junit.platform:junit-platform-launcher",
-      "org.junit.platform:junit-platform-reporting",
-      "org.opentest4j:opentest4j",
-      "org.scala-lang.modules:scala-collection-compat_2.13",
-      "org.scala-lang.modules:scala-xml_2.13",
-      "org.scala-lang:scala-compiler",
-      "org.scala-lang:scala-library",
-      "org.scala-lang:scala-reflect",
-      "org.scalactic:scalactic_2.13",
-      "org.scalameta:semanticdb-scalac_2.13.17",
-      "org.scalatest:scalatest-compatible",
-      "org.scalatest:scalatest-core_2.13",
-      "org.scalatest:scalatest-diagrams_2.13",
-      "org.scalatest:scalatest-featurespec_2.13",
-      "org.scalatest:scalatest-flatspec_2.13",
-      "org.scalatest:scalatest-freespec_2.13",
-      "org.scalatest:scalatest-funspec_2.13",
-      "org.scalatest:scalatest-funsuite_2.13",
-      "org.scalatest:scalatest-matchers-core_2.13",
-      "org.scalatest:scalatest-mustmatchers_2.13",
-      "org.scalatest:scalatest-propspec_2.13",
-      "org.scalatest:scalatest-refspec_2.13",
-      "org.scalatest:scalatest-shouldmatchers_2.13",
-      "org.scalatest:scalatest-wordspec_2.13",
-      "org.scalatest:scalatest_2.13",
-      "org.typelevel:cats-core_2.13",
-      "org.typelevel:cats-kernel_2.13",
-      "org.typelevel:jawn-parser_2.13"
-    ]
-  },
-  "services": {
-    "org.jline:jline:jar:jdk8": {
-      "org/": [],
-      "org/jline/": [],
-      "org/jline/terminal/": [],
-      "org/jline/terminal/provider/": [],
-      "org/jline/terminal/provider/exec": [
-        "class=org.jline.terminal.impl.exec.ExecTerminalProvider"
-      ],
-      "org/jline/terminal/provider/ffm": [
-        "class=org.jline.terminal.impl.ffm.FfmTerminalProvider"
-      ],
-      "org/jline/terminal/provider/jansi": [
-        "class=org.jline.terminal.impl.jansi.JansiTerminalProvider"
-      ],
-      "org/jline/terminal/provider/jna": [
-        "class=org.jline.terminal.impl.jna.JnaTerminalProvider"
-      ],
-      "org/jline/terminal/provider/jni": [
-        "class=org.jline.terminal.impl.jni.JniTerminalProvider"
-      ]
-    },
-    "org.junit.jupiter:junit-jupiter-engine": {
-      "org.junit.platform.engine.TestEngine": [
-        "org.junit.jupiter.engine.JupiterTestEngine"
-      ]
-    },
-    "org.junit.platform:junit-platform-launcher": {
-      "org.junit.platform.launcher.TestExecutionListener": [
-        "org.junit.platform.launcher.listeners.UniqueIdTrackingListener"
-      ]
-    },
-    "org.junit.platform:junit-platform-reporting": {
-      "org.junit.platform.launcher.TestExecutionListener": [
-        "org.junit.platform.reporting.open.xml.OpenTestReportGeneratingListener"
-      ]
-    },
-    "org.scala-lang:scala-compiler": {
-      "javax.script.ScriptEngineFactory": [
-        "scala.tools.nsc.interpreter.shell.Scripted$Factory"
-      ]
-    },
-    "org.scalameta:semanticdb-scalac_2.13.17": {
-      "com.sun.jdi.connect.Connector": [
-        "com.sun.tools.jdi.ProcessAttachingConnector",
-        "com.sun.tools.jdi.RawCommandLineLauncher",
-        "com.sun.tools.jdi.SocketAttachingConnector",
-        "com.sun.tools.jdi.SocketListeningConnector",
-        "com.sun.tools.jdi.SunCommandLineLauncher"
-      ],
-      "com.sun.jdi.connect.spi.TransportService": [],
-      "com.sun.tools.attach.spi.AttachProvider": [
-        "sun.tools.attach.LinuxAttachProvider"
-      ],
-      "com.sun.tools.internal.ws.wscompile.Plugin": [
-        "com.sun.tools.internal.ws.wscompile.plugin.at_generated.PluginImpl"
-      ],
-      "com.sun.tools.internal.xjc.Plugin": [
-        "com.sun.tools.internal.xjc.addon.accessors.PluginImpl",
-        "com.sun.tools.internal.xjc.addon.at_generated.PluginImpl",
-        "com.sun.tools.internal.xjc.addon.code_injector.PluginImpl",
-        "com.sun.tools.internal.xjc.addon.episode.PluginImpl",
-        "com.sun.tools.internal.xjc.addon.locator.SourceLocationAddOn",
-        "com.sun.tools.internal.xjc.addon.sync.SynchronizedMethodAddOn"
-      ],
-      "org/": [],
-      "org/jline/": [],
-      "org/jline/terminal/": [],
-      "org/jline/terminal/provider/": [],
-      "org/jline/terminal/provider/exec": [
-        "class=org.jline.terminal.impl.exec.ExecTerminalProvider"
-      ],
-      "org/jline/terminal/provider/ffm": [
-        "class=org.jline.terminal.impl.ffm.FfmTerminalProvider"
-      ],
-      "org/jline/terminal/provider/jansi": [
-        "class=org.jline.terminal.impl.jansi.JansiTerminalProvider"
-      ],
-      "org/jline/terminal/provider/jna": [
-        "class=org.jline.terminal.impl.jna.JnaTerminalProvider"
-      ],
-      "org/jline/terminal/provider/jni": [
-        "class=org.jline.terminal.impl.jni.JniTerminalProvider"
-      ]
-    }
-  },
-  "version": "2"
-}
diff --git a/rules-chisel-dev-dep.patch b/rules-chisel-dev-dep.patch
deleted file mode 100644
index 8ade9aef8bf..00000000000
--- a/rules-chisel-dev-dep.patch
+++ /dev/null
@@ -1,22 +0,0 @@
---- a/chisel/extensions.bzl
-+++ b/chisel/extensions.bzl
-@@ -170,9 +170,16 @@
-         scala_version = settings.scala_version,
-     )
-
-+    root_is_dev = True
-+    for mod in module_ctx.modules:
-+        if mod.is_root:
-+            for tag in mod.tags.toolchain:
-+                if not module_ctx.is_dev_dependency(tag):
-+                    root_is_dev = False
-+
-     return module_ctx.extension_metadata(
-         reproducible = settings.lock_file != None,
--        root_module_direct_deps = [settings.repo_name],
--        root_module_direct_dev_deps = [],
-+        root_module_direct_deps = [] if root_is_dev else [settings.repo_name],
-+        root_module_direct_dev_deps = [settings.repo_name] if root_is_dev else [],
-     )
-
- toolchain = tag_class(
diff --git a/test/orfs/mock-array/BUILD b/test/orfs/mock-array/BUILD
index 2a18d89a7df..b0629be6f58 100644
--- a/test/orfs/mock-array/BUILD
+++ b/test/orfs/mock-array/BUILD
@@ -1,5 +1,4 @@
 load("@bazel-orfs//:openroad.bzl", "orfs_run")
-load("@rules_chisel//chisel:defs.bzl", "chisel_binary")
 load("//test/orfs/asap7:asap7.bzl", "ASAP7_REMOVE_CELLS")
 load(":mock-array.bzl", "config", "element", "mock_array", "verilog")
 
@@ -9,15 +8,11 @@ package(
 
 exports_files(["write_verilog.tcl"])
 
-chisel_binary(
-    name = "generate_verilog",
-    srcs = glob(["src/main/scala/**/*.scala"]),
-    main_class = "GenerateMockArray",
-    resources = glob(["src/main/resources/**/*"]),
+# Amaranth-generated multiplier gate-level Verilog (needs native Yosys frontend)
+filegroup(
+    name = "multiplier_v",
+    srcs = ["src/main/resources/multiplier.v"],
     tags = ["manual"],
-    deps = [
-        "@maven//:com_github_scopt_scopt_2_13",
-    ],
 )
 
 filegroup(
diff --git a/test/orfs/mock-array/MockArray.sv b/test/orfs/mock-array/MockArray.sv
new file mode 100644
index 00000000000..6ce55cb2f50
--- /dev/null
+++ b/test/orfs/mock-array/MockArray.sv
@@ -0,0 +1,259 @@
+// MockArray - Idiomatic SystemVerilog rewrite of MockArray.scala
+//
+// Parameterized 2D array of Element modules, each containing 4 Multiplier
+// instances with registered crossbar routing. Used as a test design for
+// OpenROAD-flow-scripts.
+
+// Blackbox stub for the gate-level multiplier (Amaranth-generated).
+// The actual implementation lives in multiplier.v and is joined
+// after hierarchical synthesis via genrule.
+module multiplier(
+  input  logic [31:0] b,
+  input  logic        clk,
+  input  logic        rst,
+  output logic [31:0] o,
+  input  logic [31:0] a
+);
+endmodule
+
+// Multiplier wrapper - reduces blackbox output to bits [3:0].
+// Kept as a separate module for hierarchical power testing.
+module Multiplier(
+  input  logic [31:0] a,
+  input  logic [31:0] b,
+  output logic [31:0] o,
+  input  logic        rst,
+  input  logic        clk
+);
+  logic [31:0] mult_o;
+  multiplier mult_inst(
+    .a(a),
+    .b(b),
+    .o(mult_o),
+    .rst(rst),
+    .clk(clk)
+  );
+  assign o = {28'b0, mult_o[3:0]};
+endmodule
+
+// ElementInner - parameterized single cell in the MockArray grid.
+//
+// Registered crossbar routing with multipliers:
+//   out_left  = reg(mult(reg(in_down),  reg(in_left)))
+//   out_up    = reg(mult(reg(in_right), reg(in_down)))
+//   out_right = reg(mult(reg(in_up),    reg(in_right)))
+//   out_down  = reg(mult(reg(in_left),  reg(in_up)))
+//
+// LSB chain: combinational shift with a register every COLS/2 steps.
+module ElementInner #(
+  parameter int DATA_WIDTH = 64,
+  parameter int COLS       = 8
+)(
+  input  logic                  clock,
+  input  logic [DATA_WIDTH-1:0] io_ins_left,
+  input  logic [DATA_WIDTH-1:0] io_ins_up,
+  input  logic [DATA_WIDTH-1:0] io_ins_right,
+  input  logic [DATA_WIDTH-1:0] io_ins_down,
+  output logic [DATA_WIDTH-1:0] io_outs_left,
+  output logic [DATA_WIDTH-1:0] io_outs_up,
+  output logic [DATA_WIDTH-1:0] io_outs_right,
+  output logic [DATA_WIDTH-1:0] io_outs_down,
+  input  logic [COLS-1:0]       io_lsbIns,
+  output logic [COLS-1:0]       io_lsbOuts
+);
+  localparam int MAX_FLIGHT = COLS / 2;
+
+  // Stage 1: register all directional inputs
+  logic [DATA_WIDTH-1:0] left_r, up_r, right_r, down_r;
+  always_ff @(posedge clock) begin : reg_inputs
+    left_r  <= io_ins_left;
+    up_r    <= io_ins_up;
+    right_r <= io_ins_right;
+    down_r  <= io_ins_down;
+  end
+
+  // Stage 2: multiplier crossbar
+  logic [31:0] mult_left_o, mult_up_o, mult_right_o, mult_down_o;
+
+  Multiplier mult_left(
+    .a(down_r[31:0]),  .b(left_r[31:0]),
+    .o(mult_left_o),   .rst(1'b0), .clk(clock)
+  );
+  Multiplier mult_up(
+    .a(right_r[31:0]), .b(down_r[31:0]),
+    .o(mult_up_o),     .rst(1'b0), .clk(clock)
+  );
+  Multiplier mult_right(
+    .a(up_r[31:0]),    .b(right_r[31:0]),
+    .o(mult_right_o),  .rst(1'b0), .clk(clock)
+  );
+  Multiplier mult_down(
+    .a(left_r[31:0]),  .b(up_r[31:0]),
+    .o(mult_down_o),   .rst(1'b0), .clk(clock)
+  );
+
+  // Stage 3: register multiplier outputs (zero-extended to DATA_WIDTH)
+  always_ff @(posedge clock) begin : reg_outputs
+    io_outs_left  <= mult_left_o;
+    io_outs_up    <= mult_up_o;
+    io_outs_right <= mult_right_o;
+    io_outs_down  <= mult_down_o;
+  end
+
+  // LSB chain: shift lsbIns left by one position.
+  // Insert a register break every MAX_FLIGHT positions to limit
+  // combinational path length to COLS/2 elements.
+  logic [COLS-1:0] lsb_reg;
+  always_ff @(posedge clock) begin : reg_lsb
+    for (int j = 0; j < COLS - 1; j++) begin
+      if ((COLS - 1 - j) % MAX_FLIGHT == 0)
+        lsb_reg[j] <= io_lsbIns[j + 1];
+    end
+  end
+
+  always_comb begin : comb_lsb
+    for (int j = 0; j < COLS - 1; j++) begin
+      if ((COLS - 1 - j) % MAX_FLIGHT == 0)
+        io_lsbOuts[j] = lsb_reg[j];
+      else
+        io_lsbOuts[j] = io_lsbIns[j + 1];
+    end
+    io_lsbOuts[COLS - 1] = io_outs_left[0];
+  end
+endmodule
+
+// Element - concrete wrapper for synthesis as a standalone macro.
+// Uses `define to set COLS per config since OpenROAD cannot read
+// parameterized Verilog instantiations.
+//
+// ELEMENT_COLS must be defined at synthesis time via -D flag, e.g.:
+//   SYNTH_SLANG_ARGS: "-DELEMENT_COLS=4"
+`ifndef ELEMENT_COLS
+`define ELEMENT_COLS 8
+`endif
+module Element(
+  input  logic        clock,
+  input  logic [63:0] io_ins_left,
+  input  logic [63:0] io_ins_up,
+  input  logic [63:0] io_ins_right,
+  input  logic [63:0] io_ins_down,
+  output logic [63:0] io_outs_left,
+  output logic [63:0] io_outs_up,
+  output logic [63:0] io_outs_right,
+  output logic [63:0] io_outs_down,
+  input  logic [`ELEMENT_COLS-1:0] io_lsbIns,
+  output logic [`ELEMENT_COLS-1:0] io_lsbOuts
+);
+  ElementInner #(.DATA_WIDTH(64), .COLS(`ELEMENT_COLS)) inner(.*);
+endmodule
+
+// MockArray - parameterized 2D array of Elements
+module MockArray #(
+  parameter int WIDTH      = 8,
+  parameter int HEIGHT     = 8,
+  parameter int DATA_WIDTH = 64
+)(
+  input  logic                  clock,
+  input  logic                  reset,
+  input  logic [DATA_WIDTH-1:0] io_ins_left   [HEIGHT],
+  input  logic [DATA_WIDTH-1:0] io_ins_right  [HEIGHT],
+  input  logic [DATA_WIDTH-1:0] io_ins_up     [WIDTH],
+  input  logic [DATA_WIDTH-1:0] io_ins_down   [WIDTH],
+  output logic [DATA_WIDTH-1:0] io_outs_left  [HEIGHT],
+  output logic [DATA_WIDTH-1:0] io_outs_right [HEIGHT],
+  output logic [DATA_WIDTH-1:0] io_outs_up    [WIDTH],
+  output logic [DATA_WIDTH-1:0] io_outs_down  [WIDTH],
+  output logic [WIDTH*HEIGHT-1:0] io_lsbs
+);
+
+  // Element grid interconnect
+  logic [DATA_WIDTH-1:0] e_ins_left   [HEIGHT][WIDTH];
+  logic [DATA_WIDTH-1:0] e_ins_up     [HEIGHT][WIDTH];
+  logic [DATA_WIDTH-1:0] e_ins_right  [HEIGHT][WIDTH];
+  logic [DATA_WIDTH-1:0] e_ins_down   [HEIGHT][WIDTH];
+  logic [DATA_WIDTH-1:0] e_outs_left  [HEIGHT][WIDTH];
+  logic [DATA_WIDTH-1:0] e_outs_up    [HEIGHT][WIDTH];
+  logic [DATA_WIDTH-1:0] e_outs_right [HEIGHT][WIDTH];
+  logic [DATA_WIDTH-1:0] e_outs_down  [HEIGHT][WIDTH];
+  logic [WIDTH-1:0]      e_lsbIns     [HEIGHT][WIDTH];
+  logic [WIDTH-1:0]      e_lsbOuts    [HEIGHT][WIDTH];
+
+  // Instantiate Element grid. Generate labels must be unique within
+  // their enclosing scope; the instance name ces keeps the leaf
+  // identifier matching the power/parasitics scripts.
+  for (genvar r = 0; r < HEIGHT; r++) begin : ces_row
+    for (genvar c = 0; c < WIDTH; c++) begin : ces_col
+      // Element parameters (DATA_WIDTH, COLS) are set via
+      // VERILOG_TOP_PARAMS at synthesis time - do not override here
+      // as OpenROAD cannot read parameterized instantiations.
+      Element ces(
+        .clock       (clock),
+        .io_ins_left (e_ins_left  [r][c]),
+        .io_ins_up   (e_ins_up    [r][c]),
+        .io_ins_right(e_ins_right [r][c]),
+        .io_ins_down (e_ins_down  [r][c]),
+        .io_outs_left (e_outs_left [r][c]),
+        .io_outs_up   (e_outs_up   [r][c]),
+        .io_outs_right(e_outs_right[r][c]),
+        .io_outs_down (e_outs_down [r][c]),
+        .io_lsbIns   (e_lsbIns    [r][c]),
+        .io_lsbOuts  (e_lsbOuts   [r][c])
+      );
+    end
+  end
+
+  // --- Edge connectivity: top-level inputs to border elements ---
+  for (genvar r = 0; r < HEIGHT; r++) begin : gen_edge_lr
+    assign e_ins_right[r][0]        = io_ins_right[r];
+    assign e_ins_left [r][WIDTH-1]  = io_ins_left[r];
+  end
+  for (genvar c = 0; c < WIDTH; c++) begin : gen_edge_ud
+    assign e_ins_down[HEIGHT-1][c]  = io_ins_down[c];
+    assign e_ins_up  [0][c]         = io_ins_up[c];
+  end
+
+  // --- Edge connectivity: border elements to top-level outputs ---
+  for (genvar r = 0; r < HEIGHT; r++) begin : gen_out_lr
+    assign io_outs_left [r] = e_outs_left [r][0];
+    assign io_outs_right[r] = e_outs_right[r][WIDTH-1];
+  end
+  for (genvar c = 0; c < WIDTH; c++) begin : gen_out_ud
+    assign io_outs_up  [c] = e_outs_up  [HEIGHT-1][c];
+    assign io_outs_down[c] = e_outs_down[0][c];
+  end
+
+  // --- Neighbor connectivity: left/right ---
+  for (genvar r = 0; r < HEIGHT; r++) begin : gen_nb_lr
+    for (genvar c = 0; c < WIDTH - 1; c++) begin : gen_nb_col
+      assign e_ins_left [r][c]   = e_outs_left [r][c+1];
+      assign e_ins_right[r][c+1] = e_outs_right[r][c];
+    end
+  end
+
+  // --- Neighbor connectivity: up/down ---
+  for (genvar r = 0; r < HEIGHT - 1; r++) begin : gen_nb_ud
+    for (genvar c = 0; c < WIDTH; c++) begin : gen_nb_col
+      assign e_ins_down[r][c]   = e_outs_down[r+1][c];
+      assign e_ins_up  [r+1][c] = e_outs_up  [r][c];
+    end
+  end
+
+  // --- LSB chain: left-to-right within each row ---
+  for (genvar r = 0; r < HEIGHT; r++) begin : gen_lsb_chain
+    assign e_lsbIns[r][0] = '0;
+    for (genvar c = 1; c < WIDTH; c++) begin : gen_lsb_col
+      assign e_lsbIns[r][c] = e_lsbOuts[r][c-1];
+    end
+  end
+
+  // --- Output LSBs: registered last-column lsbOuts ---
+  logic [WIDTH*HEIGHT-1:0] lsbs_pre;
+  for (genvar r = 0; r < HEIGHT; r++) begin : gen_lsbs_concat
+    assign lsbs_pre[r*WIDTH +: WIDTH] = e_lsbOuts[r][WIDTH-1];
+  end
+  always_ff @(posedge clock) begin : reg_lsbs
+    io_lsbs <= lsbs_pre;
+  end
+
+endmodule
+
diff --git a/test/orfs/mock-array/README.md b/test/orfs/mock-array/README.md
index 0f599716043..21cea39849a 100644
--- a/test/orfs/mock-array/README.md
+++ b/test/orfs/mock-array/README.md
@@ -140,10 +140,6 @@ Hierarchical synthesis uses three separate Yosys runs stitched together:
 # Quick: analysis only (no build), checks for Bazel conflicts
 bazelisk build --nobuild //test/orfs/mock-array:all
 
-# Fast: interface comparison (SV vs Chisel reference)
-bazelisk test //test/orfs/mock-array:compare_interfaces_4x4
-bazelisk test //test/orfs/mock-array:compare_interfaces_8x8
-
 # Medium: synthesis only
 bazelisk build //test/orfs/mock-array:MockArray_4x4_slang_synth
 bazelisk build //test/orfs/mock-array:Element_4x4_slang_synth
diff --git a/test/orfs/mock-array/check_macro_layout.tcl b/test/orfs/mock-array/check_macro_layout.tcl
new file mode 100644
index 00000000000..69a2981f614
--- /dev/null
+++ b/test/orfs/mock-array/check_macro_layout.tcl
@@ -0,0 +1,120 @@
+source $::env(SCRIPTS_DIR)/load.tcl
+
+load_design 2_floorplan.odb 2_floorplan.sdc
+
+set rows $::env(ARRAY_ROWS)
+set cols $::env(ARRAY_COLS)
+set expected [expr { $rows * $cols }]
+
+set block [ord::get_db_block]
+
+set elements [list]
+foreach inst [$block getInsts] {
+  set master [$inst getMaster]
+  if { ![$master isBlock] } {
+    continue
+  }
+  if { [$master getName] ne "Element" } {
+    continue
+  }
+  lappend elements $inst
+}
+
+set count [llength $elements]
+if { $count != $expected } {
+  puts "ERROR: expected $expected Element macros (${rows}x${cols}), found $count"
+  foreach inst $elements {
+    puts "  [$inst getName]"
+  }
+  exit 1
+}
+
+# Collect (xMin, yMin, orient, name, width, height) from oriented bboxes.
+set entries [list]
+set first_orient ""
+set macro_width ""
+set macro_height ""
+foreach inst $elements {
+  set bbox [$inst getBBox]
+  set x [$bbox xMin]
+  set y [$bbox yMin]
+  set w [$bbox getDX]
+  set h [$bbox getDY]
+  set orient [$inst getOrient]
+  if { $first_orient eq "" } {
+    set first_orient $orient
+    set macro_width $w
+    set macro_height $h
+  } elseif { $orient ne $first_orient } {
+    puts "ERROR: Element [$inst getName] has orientation $orient,\
+      expected $first_orient (all macros must share orientation)"
+    exit 1
+  }
+  lappend entries [list $x $y $orient [$inst getName] $w $h]
+}
+
+# Group by row (unique yMin). Row 0 = minimum Y = bottom.
+set rows_map [dict create]
+foreach e $entries {
+  set y [lindex $e 1]
+  dict lappend rows_map $y $e
+}
+
+set row_ys [lsort -integer [dict keys $rows_map]]
+if { [llength $row_ys] != $rows } {
+  puts "ERROR: expected $rows distinct row Y positions, found [llength $row_ys]: $row_ys"
+  foreach y $row_ys {
+    puts "  y=$y count=[llength [dict get $rows_map $y]]"
+  }
+  exit 1
+}
+
+# Each row must have exactly `cols` macros; capture X positions per row.
+set row_x_lists [list]
+foreach y $row_ys {
+  set row_entries [dict get $rows_map $y]
+  if { [llength $row_entries] != $cols } {
+    puts "ERROR: row at y=$y has [llength $row_entries] macros, expected $cols"
+    foreach e $row_entries {
+      puts "  [lindex $e 3] at ([lindex $e 0], [lindex $e 1])"
+    }
+    exit 1
+  }
+  set xs [list]
+  foreach e [lsort -integer -index 0 $row_entries] {
+    lappend xs [lindex $e 0]
+  }
+  lappend row_x_lists $xs
+}
+
+# Columns must align across rows.
+set ref_xs [lindex $row_x_lists 0]
+for { set r 1 } { $r < $rows } { incr r } {
+  set xs [lindex $row_x_lists $r]
+  if { $xs ne $ref_xs } {
+    puts "ERROR: column X positions differ between row 0 and row $r (y=[lindex $row_ys $r])"
+    puts "  row 0: $ref_xs"
+    puts "  row $r: $xs"
+    exit 1
+  }
+}
+
+# Abutment: consecutive column X values must differ by exactly macro_width.
+for { set c 1 } { $c < $cols } { incr c } {
+  set dx [expr { [lindex $ref_xs $c] - [lindex $ref_xs [expr { $c - 1 }]] }]
+  if { $dx != $macro_width } {
+    puts "ERROR: columns [expr { $c - 1 }] and $c not abutted: dx=$dx, macro_width=$macro_width"
+    puts "  column X positions: $ref_xs"
+    exit 1
+  }
+}
+
+puts "OK: ${rows}x${cols} Element macros in grid"
+puts "  orientation: $first_orient"
+puts "  macro size (DBU): ${macro_width} x ${macro_height}"
+puts "  row Y (bottom to top): $row_ys"
+puts "  col X (left to right): $ref_xs"
+
+set f [open $::env(OUTPUT) w]
+puts $f "OK"
+close $f
diff --git a/test/orfs/mock-array/element-io.tcl b/test/orfs/mock-array/element-io.tcl
index e35d6fd4f0f..8c4ee21f619 100644
--- a/test/orfs/mock-array/element-io.tcl
+++ b/test/orfs/mock-array/element-io.tcl
@@ -17,9 +17,9 @@ set assignments [list \
       {*}[match_pins io_ins_left.*]]] \
   left right \
   [list [concat \
-    {*}[match_pins io_lsbIns_.*]] \
+    {*}[match_pins io_lsbIns.*]] \
     [concat \
-      {*}[match_pins io_lsbOuts_.*]]]]
+      {*}[match_pins io_lsbOuts.*]]]]
 
 proc zip { list1 list2 } {
   set result {}
diff --git a/test/orfs/mock-array/io.tcl b/test/orfs/mock-array/io.tcl
index 55695bf1e14..7b8633c928e 100644
--- a/test/orfs/mock-array/io.tcl
+++ b/test/orfs/mock-array/io.tcl
@@ -3,21 +3,21 @@ source test/orfs/mock-array/util.tcl
 set assignments [list \
   top \
   [concat \
-    {*}[match_pins io_ins_down_.*] \
-    {*}[match_pins io_outs_up_.*]] \
+    {*}[match_pins io_ins_down.*] \
+    {*}[match_pins io_outs_up.*]] \
   bottom \
   [concat \
-    {*}[match_pins io_ins_up_.*] \
-    {*}[match_pins io_outs_down_.*]] \
+    {*}[match_pins io_ins_up.*] \
+    {*}[match_pins io_outs_down.*]] \
   left \
   [concat \
-    {*}[match_pins io_ins_right_.*] \
-    {*}[match_pins io_outs_left_.*]] \
+    {*}[match_pins io_ins_right.*] \
+    {*}[match_pins io_outs_left.*]] \
   right \
   [concat \
-    {*}[match_pins io_ins_left_.*] \
-    {*}[match_pins io_outs_right_.*] \
-    {*}[match_pins io_lsbs_.*]]]
+    {*}[match_pins io_ins_left.*] \
+    {*}[match_pins io_outs_right.*] \
+    {*}[match_pins io_lsbs.*]]]
 
 foreach {direction names} $assignments {
   set_io_pin_constraint -region $direction:* -pin_names $names
diff --git a/test/orfs/mock-array/load_mock_array.tcl b/test/orfs/mock-array/load_mock_array.tcl
index d0e7ec89913..afab8569838 100644
--- a/test/orfs/mock-array/load_mock_array.tcl
+++ b/test/orfs/mock-array/load_mock_array.tcl
@@ -37,7 +37,9 @@ proc check_log_for_warning { logfile } {
 set name [lindex [split $::env(FLOW_VARIANT) "_"] 0]
 
 log_cmd read_verilog $::env(RESULTS_DIR)/$::env(POWER_STAGE_STEM).v
-log_cmd read_verilog $::env(RESULTS_DIR)/../../Element/${name}_base/$::env(POWER_STAGE_STEM).v
+if { [string match "*_base" $::env(FLOW_VARIANT)] } {
+  log_cmd read_verilog $::env(RESULTS_DIR)/../../Element/${name}_base/$::env(POWER_STAGE_STEM).v
+}
 log_cmd read_verilog $::env(PLATFORM_DIR)/verilog/stdcell/empty.v
 if { [string match "*openroad" $::env(OPENROAD_EXE)] } {
   log_cmd link_design -hier MockArray
@@ -49,11 +51,14 @@ log_cmd read_sdc $::env(RESULTS_DIR)/$::env(POWER_STAGE_STEM).sdc
 log_cmd read_spef $::env(RESULTS_DIR)/$::env(POWER_STAGE_STEM).spef > log.txt
 check_log_for_warning log.txt
 
-puts "read_spef for ces_*_* macros"
-for { set x 0 } { $x < $::env(ARRAY_COLS) } { incr x } {
-  for { set y 0 } { $y < $::env(ARRAY_ROWS) } { incr y } {
-    log_cmd read_spef -path ces_${x}_${y} \
-      $::env(RESULTS_DIR)/../../Element/${name}_base/$::env(POWER_STAGE_STEM).spef > log.txt
-    check_log_for_warning log.txt
+# Only read per-Element SPEF for hierarchical (base) variant
+if { [string match "*_base" $::env(FLOW_VARIANT)] } {
+  puts "read_spef for Element macros"
+  for { set r 0 } { $r < $::env(ARRAY_ROWS) } { incr r } {
+    for { set c 0 } { $c < $::env(ARRAY_COLS) } { incr c } {
+      log_cmd read_spef -path "ces_row\[${r}\].ces_col\[${c}\].ces" \
+        $::env(RESULTS_DIR)/../../Element/${name}_base/$::env(POWER_STAGE_STEM).spef > log.txt
+      check_log_for_warning log.txt
+    }
   }
 }
diff --git a/test/orfs/mock-array/mock-array.bzl b/test/orfs/mock-array/mock-array.bzl
index 6734da1b123..0d5cc6b3f8e 100644
--- a/test/orfs/mock-array/mock-array.bzl
+++ b/test/orfs/mock-array/mock-array.bzl
@@ -2,73 +2,117 @@
 Generates mock-array test cases
 """
 
-load("@bazel-orfs//:openroad.bzl", "orfs_flow", "orfs_run")
-load("@bazel-orfs-verilog//:generate.bzl", "fir_library")
-load("@bazel-orfs-verilog//:verilog.bzl", "verilog_directory", "verilog_single_file_library")
+load("@bazel-orfs//:openroad.bzl", "orfs_flow", "orfs_run", "orfs_synth")
 load("@rules_cc//cc:defs.bzl", "cc_binary")
 load("@rules_shell//shell:sh_test.bzl", "sh_test")
 load("@rules_verilator//verilator:defs.bzl", "verilator_cc_library")
 load("@rules_verilator//verilog:defs.bzl", "verilog_library")
 load("//test/orfs:eqy-flow.bzl", "eqy_flow_test")
 
-FIRTOOL_OPTIONS = [
-    "-disable-all-randomization",
-    "-strip-debug-info",
-    "-enable-layers=Verification",
-    "-enable-layers=Verification.Assert",
-    "-enable-layers=Verification.Assume",
-    "-enable-layers=Verification.Cover",
-]
-
-def verilog(name, rows, cols):
-    """Generate mock array verilog
+def verilog(name, **_kwargs):
+    """Provide mock array verilog sources
 
     Args:
         name: Name of the verilog target
-        rows: Number of rows in the array
-        cols: Number of columns in the array
+        **_kwargs: Unused, kept for call-site compatibility
     """
 
-    fir_library(
-        name = "generate_{name}_fir".format(name = name),
-        data = [
+    # RTL only (for slang synthesis - multiplier is blackboxed)
+    native.filegroup(
+        name = "{name}_rtl".format(name = name),
+        srcs = [
+            "MockArray.sv",
         ],
-        generator = "//test/orfs/mock-array:generate_verilog",
-        opts = [
-            "--width=" + str(cols),
-            "--height=" + str(rows),
-            "--dataWidth=64",
-            "--",
-            # Imagine Chisel arguments here
-            "--",
-        ] + FIRTOOL_OPTIONS,
         tags = ["manual"],
     )
 
-    verilog_directory(
-        name = "generate_{name}_split".format(name = name),
-        srcs = [":generate_{name}_fir".format(name = name)],
-        opts = FIRTOOL_OPTIONS,
+    # Full sources including gate-level multiplier (for simulation and eqy)
+    native.filegroup(
+        name = "{name}_verilog".format(name = name),
+        srcs = [
+            "src/main/resources/multiplier.v",
+            "MockArray.sv",
+        ],
         tags = ["manual"],
     )
 
-    verilog_single_file_library(
-        name = "{name}_array.sv".format(name = name),
-        srcs = [":generate_{name}_split".format(name = name)],
+def element(name, config):
+    """Synthesize and place-and-route a single Element of the mock array.
+
+    Args:
+      name: Name of the element configuration.
+      config: Configuration object from config().
+    """
+
+    # Hierarchical synthesis:
+    #  1. Synthesize Element RTL with slang (multiplier blackboxed)
+    #  2. Synthesize multiplier.v with native Yosys (Amaranth-generated
+    #     Verilog triggers a yosys-slang assertion with --keep-hierarchy)
+    #  3. Cat the two netlists together
+    #
+    # This also serves as a test for hierarchical synthesis in OpenROAD.
+    orfs_synth(
+        name = "Element_{name}_slang_synth".format(name = name),
+        arguments = {
+            "SYNTH_BLACKBOXES": "multiplier",
+            "SYNTH_HDL_FRONTEND": "slang",
+            "SYNTH_SLANG_ARGS": "--ignore-unknown-modules --empty-blackboxes -DELEMENT_COLS={}".format(config["cols"]),
+        },
+        module_top = "Element",
+        save_odb = False,
+        sources = {
+            "SDC_FILE": [":mock-array-constraints"],
+        },
         tags = ["manual"],
-        visibility = ["//visibility:public"],
+        variant = "{name}_slang".format(name = name),
+        verilog_files = [":{name}_rtl".format(name = name)],
     )
 
     native.filegroup(
-        name = "{name}_verilog".format(name = name),
+        name = "Element_{name}_slang_netlist".format(name = name),
+        srcs = [":Element_{name}_slang_synth".format(name = name)],
+        output_group = "1_2_yosys.v",
+        tags = ["manual"],
+    )
+
+    # Synthesize multiplier.v with native Yosys frontend (not slang).
+    # multiplier.v is Amaranth-generated gate-level Verilog with behavioral
+    # constructs (reg = value) that OpenROAD's reader cannot parse directly.
+    orfs_synth(
+        name = "multiplier_{name}_synth".format(name = name),
+        arguments = {
+            "SYNTH_HDL_FRONTEND": "",
+        },
+        module_top = "multiplier",
+        save_odb = False,
+        sources = {
+            "SDC_FILE": [":mock-array-constraints"],
+        },
+        tags = ["manual"],
+        variant = "{name}".format(name = name),
+        verilog_files = [":multiplier_v"],
+    )
+
+    native.filegroup(
+        name = "multiplier_{name}_netlist".format(name = name),
+        srcs = [":multiplier_{name}_synth".format(name = name)],
+        output_group = "1_2_yosys.v",
+        tags = ["manual"],
+    )
+
+    # Combine the slang-synthesized Element netlist with the
+    # Yosys-processed multiplier netlist.
+    native.genrule(
+        name = "Element_{name}_combined_netlist".format(name = name),
         srcs = [
-            "src/main/resources/multiplier.v",
-            ":{name}_array.sv".format(name = name),
+            ":Element_{name}_slang_netlist".format(name = name),
+            ":multiplier_{name}_netlist".format(name = name),
         ],
+        outs = ["Element_{name}_combined_netlist.v".format(name = name)],
+        cmd = "cat $(SRCS) > $@",
         tags = ["manual"],
     )
 
-def element(name, config):
     orfs_flow(
         name = "Element",
         arguments = {
@@ -88,20 +132,17 @@ def element(name, config):
             "IO_PLACER_V": "M3 M5",
             "MAX_ROUTING_LAYER": "M5",
             "MIN_ROUTING_LAYER": "M2",
-            # We want to report power per module using hierarhical .odb
+            # We want to report power per module using hierarchical .odb
             "OPENROAD_HIERARCHICAL": "1",
             "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl",
             "PLACE_DENSITY": "0.82",
             "PLACE_PINS_ARGS": "-annealing",
             "PWR_NETS_VOLTAGES": "",
-            # Keep only one module, enough for testing, faster builds. There's
-            # some width in multiply reduction going on here to speed up
-            # builds, so we want to keep this exact module.
-            "SYNTH_KEEP_MODULES": "Multiplier",
         },
         sources = {
             "IO_CONSTRAINTS": [":mock-array-element-io"],
             "SDC_FILE": [":mock-array-constraints"],
+            "SYNTH_NETLIST_FILES": [":Element_{name}_combined_netlist".format(name = name)],
         },
         tags = ["manual"],
         verilog_files = [":{name}_verilog".format(name = name)],
@@ -168,7 +209,7 @@ array_spacing_x = placement_grid_x * 4
 array_spacing_y = placement_grid_y * 4
 
 def config(name, rows, cols):
-    """Generate mock array co   nfiguration object
+    """Generate mock array configuration object
 
     Args:
         name: Name of the configuration
@@ -233,8 +274,11 @@ POWER_TESTS = [
     "path_groups",
 ]
 
+# TODO: Element power tests need VCD from Verilator simulation,
+# but Verilator can't compile uniquified post-P&R base netlists
+# (each Element gets a unique module name after CTS).
 ELEMENT_POWER_TESTS = [
-    "power_modules",
+    # "power_modules",
 ]
 
 def mock_array(name, config):
@@ -250,10 +294,56 @@ def mock_array(name, config):
         "flat",
     ]}
 
+    # Hierarchical synthesis for MockArray: synthesize RTL with slang
+    # (multiplier blackboxed), then join with multiplier gate-level netlist.
+    orfs_synth(
+        name = "MockArray_{name}_slang_synth".format(name = name),
+        arguments = {
+            "SYNTH_BLACKBOXES": "multiplier Element",
+            "SYNTH_HDL_FRONTEND": "slang",
+            "SYNTH_SLANG_ARGS": "--ignore-unknown-modules --empty-blackboxes -DELEMENT_COLS={}".format(config["cols"]),
+            "VERILOG_TOP_PARAMS": "WIDTH {} HEIGHT {} DATA_WIDTH 64".format(
+                config["cols"],
+                config["rows"],
+            ),
+        },
+        module_top = "MockArray",
+        save_odb = False,
+        sources = {
+            "SDC_FILE": [":mock-array-constraints"],
+        },
+        tags = ["manual"],
+        variant = "{name}_netlist".format(name = name),
+        verilog_files = [":{name}_rtl".format(name = name)],
+    )
+
+    native.filegroup(
+        name = "MockArray_{name}_slang_netlist".format(name = name),
+        srcs = [":MockArray_{name}_slang_synth".format(name = name)],
+        output_group = "1_2_yosys.v",
+        tags = ["manual"],
+    )
+
+    # Element is supplied as a LEF/LIB macro abstract via the `macros`
+    # attribute, so the netlist must leave Element (and its inner
+    # multiplier) as unresolved references. If the full Element body is
+    # concatenated here, OpenROAD links against the Verilog hierarchy
+    # instead of the macro abstract and the N x N grid of Element macros
+    # collapses into flattened std cells at floorplan time. The same
+    # netlist is used for both variants; base vs flat differ only in
+    # OPENROAD_HIERARCHICAL.
+    native.alias(
+        name = "MockArray_{name}_netlist".format(name = name),
+        actual = ":MockArray_{name}_slang_netlist".format(name = name),
+        tags = ["manual"],
+    )
+
     for v, variant in variants.items():
         orfs_flow(
             name = "MockArray",
             arguments = {
+                "ARRAY_COLS": str(config["cols"]),
+                "ARRAY_ROWS": str(config["rows"]),
                 "CORE_AREA": "{} {} {} {}".format(
                     array_spacing_x,
                     array_spacing_y,
@@ -289,11 +379,12 @@ def mock_array(name, config):
             macros = ["Element_{name}_base_generate_abstract".format(name = name)],
             sources = {
                 "IO_CONSTRAINTS": [":mock-array-io"],
+                "MACRO_PLACEMENT_TCL": [":place_mock_array.tcl"],
                 "RULES_JSON": [":rules-{variant}.json".format(variant = variant)],
                 "SDC_FILE": [":mock-array-constraints"],
+                "SYNTH_NETLIST_FILES": [":MockArray_{name}_netlist".format(name = name)],
             } | ({
                 "IO_CONSTRAINTS": [":write_pin_placement"],
-                "MACRO_PLACEMENT_TCL": [":write_macro_placement"],
             } if variant == "4x4_flat" else {}),
             tags = ["manual"],
             test_kwargs = {
@@ -353,94 +444,88 @@ def mock_array(name, config):
                         output_group = POWER_STAGE_STEM[stage] + ".v",
                     )
 
-        for stage in POWER_STAGES:
-            verilog_library(
-                name = "array_{variant}_{stage}".format(variant = variant, stage = stage),
-                srcs = [
-                    ("results/asap7/{macro}/{variant}/{stem}.v".format(
-                        macro = macro,
-                        variant = (name + "_base") if macro == "Element" else variant,
-                        stem = POWER_STAGE_STEM[stage],
-                    ) if stage != "final" else "{variant}_{macro}_netlist".format(
-                        macro = macro,
-                        variant = (name + "_base") if macro == "Element" else variant,
-                    ))
-                    for macro in MACROS
-                ] + [
-                    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_AO_RVT_TT_201020.v",
-                    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_INVBUF_RVT_TT_201020.v",
-                    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_SIMPLE_RVT_TT_201020.v",
-                    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/dff.v",
-                    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/empty.v",
-                ],
-                tags = ["manual"],
-            )
+        # Verilator simulation and VCD-based power tests only work for
+        # flat variants. The base variant's post-P&R netlists have
+        # uniquified module names that Verilator cannot handle.
+        if v != "base":
+            for stage in POWER_STAGES:
+                verilog_library(
+                    name = "array_{variant}_{stage}".format(variant = variant, stage = stage),
+                    srcs = [
+                        ("results/asap7/{macro}/{variant}/{stem}.v".format(
+                            macro = macro,
+                            variant = (name + "_base") if macro == "Element" else variant,
+                            stem = POWER_STAGE_STEM[stage],
+                        ) if stage != "final" else "{variant}_{macro}_netlist".format(
+                            macro = macro,
+                            variant = (name + "_base") if macro == "Element" else variant,
+                        ))
+                        for macro in MACROS
+                    ] + [
+                        "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_AO_RVT_TT_201020.v",
+                        "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_INVBUF_RVT_TT_201020.v",
+                        "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_SIMPLE_RVT_TT_201020.v",
+                        "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/dff.v",
+                        "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/empty.v",
+                    ],
+                    tags = ["manual"],
+                )
 
-            verilator_cc_library(
-                name = "array_verilator_{variant}_{stage}".format(variant = variant, stage = stage),
-                copts = [
-                    # Don't care about warnings from Verilator generated C++
-                    "-Wno-unused-variable",
-                ],
-                module = ":array_{variant}_{stage}".format(variant = variant, stage = stage),
-                module_top = "MockArray",
-                tags = ["manual"],
-                trace = True,
-                vopts = [
-                    "--timescale 1ps/1ps",
-                    "-Wall",
-                    "-Wno-DECLFILENAME",
-                    "-Wno-UNUSEDSIGNAL",
-                    "-Wno-PINMISSING",
-                    "--trace-underscore",
-                    # inline all PDK modules to speed up compilation
-                    "--flatten",
-                    # No-op option to retrigger a build
-                    # "-Wfuture-blah",
-                ],
-            )
+                verilator_cc_library(
+                    name = "array_verilator_{variant}_{stage}".format(variant = variant, stage = stage),
+                    copts = [
+                        # Don't care about warnings from Verilator generated C++
+                        "-Wno-unused-variable",
+                    ],
+                    module = ":array_{variant}_{stage}".format(variant = variant, stage = stage),
+                    module_top = "MockArray",
+                    tags = ["manual"],
+                    trace = True,
+                    vopts = [
+                        "--timescale 1ps/1ps",
+                        "-Wall",
+                        "-Wno-DECLFILENAME",
+                        "-Wno-UNUSEDSIGNAL",
+                        "-Wno-PINMISSING",
+                        "--trace-underscore",
+                        # inline all PDK modules to speed up compilation
+                        "--flatten",
+                        # No-op option to retrigger a build
+                        # "-Wfuture-blah",
+                    ],
+                )
 
-            cc_binary(
-                name = "simulator_{variant}_{stage}".format(variant = variant, stage = stage),
-                srcs = [
-                    "simulate.cpp",
-                ],
-                # Best way to refer to static names in Verilator generated code?
-                copts = [
-                    "-DARRAY_COLS=\"{}\"".format(
-                        ",".join([
-                            "&top->io_ins_down_{col}, &top->io_ins_up_{col}".format(col = col)
-                            for col in range(config["cols"])
-                        ]),
-                    ),
-                    "-DARRAY_ROWS=\"{}\"".format(
-                        ",".join([
-                            "&top->io_ins_left_{row}, &top->io_ins_right_{row}".format(row = row)
-                            for row in range(config["rows"])
-                        ]),
-                    ),
-                ],
-                cxxopts = [
-                    "-std=c++23",
-                ],
-                tags = ["manual"],
-                deps = [
-                    ":array_verilator_{variant}_{stage}".format(variant = variant, stage = stage),
-                ],
-            )
+                cc_binary(
+                    name = "simulator_{variant}_{stage}".format(variant = variant, stage = stage),
+                    srcs = [
+                        "simulate.cpp",
+                    ],
+                    # Best way to refer to static names in Verilator generated code?
+                    copts = [
+                        "-DARRAY_COLS={}".format(config["cols"]),
+                        "-DARRAY_ROWS={}".format(config["rows"]),
+                    ],
+                    cxxopts = [
+                        "-std=c++23",
+                    ],
+                    tags = ["manual"],
+                    deps = [
+                        ":array_verilator_{variant}_{stage}".format(variant = variant, stage = stage),
+                    ],
+                )
 
-            native.genrule(
-                name = "vcd_{variant}_{stage}".format(variant = variant, stage = stage),
-                srcs = [
-                    # FIXME move to tools, using target configuration for now to avoid rebuilds
-                    ":simulator_{variant}_{stage}".format(variant = variant, stage = stage),
-                ],
-                outs = ["MockArrayTestbench_{variant}_{stage}.vcd".format(variant = variant, stage = stage)],
-                cmd = "$(execpath :simulator_{variant}_{stage}) $(location :MockArrayTestbench_{variant}_{stage}.vcd)".format(variant = variant, stage = stage),
-                tags = ["manual"],
-                tools = [
-                ],
-            )
+                native.genrule(
+                    name = "vcd_{variant}_{stage}".format(variant = variant, stage = stage),
+                    srcs = [
+                        # FIXME move to tools, using target configuration for now to avoid rebuilds
+                        ":simulator_{variant}_{stage}".format(variant = variant, stage = stage),
+                    ],
+                    outs = ["MockArrayTestbench_{variant}_{stage}.vcd".format(variant = variant, stage = stage)],
+                    cmd = "$(execpath :simulator_{variant}_{stage}) $(location :MockArrayTestbench_{variant}_{stage}.vcd)".format(variant = variant, stage = stage),
+                    tags = ["manual"],
+                    tools = [
+                    ],
+                )
 
         # If we want to measure power after final, instead of with estimated parasitics,
         # we'll need this.
@@ -461,6 +546,14 @@ def mock_array(name, config):
         ]
 
         for power_test in POWER_TESTS:
+            # VCD-based power tests need Verilator simulation:
+            #  - base: Verilator can't handle uniquified post-P&R modules
+            #  - flat: VCD hierarchical names don't map to flat netlist
+            #          escaped wire names (e.g. \ces_row[0].ces_col[0].ces/...)
+            # Only path_groups (timing-only, no VCD) works for both.
+            needs_vcd = power_test in ("openroad", "power", "power_instances")
+            if needs_vcd:
+                continue
             for stage in POWER_STAGES:
                 orfs_run(
                     name = "MockArray_{variant}_{stage}_{power_test}".format(
@@ -487,8 +580,9 @@ def mock_array(name, config):
                         ),
                         "POWER_STAGE_NAME": stage,
                         "POWER_STAGE_STEM": POWER_STAGE_STEM[stage],
+                    } | ({
                         "VCD_STIMULI": "$(location :vcd_{variant}_{stage})".format(variant = variant, stage = stage),
-                    } | ({"openroad": {}}.get(
+                    } if needs_vcd else {}) | ({"openroad": {}}.get(
                         power_test,
                         {
                             "OPENROAD_EXE": "$(location //src/sta:opensta)",
@@ -497,9 +591,10 @@ def mock_array(name, config):
                     data = [
                                # FIXME this is a workaround to ensure that the OpenSTA runfiles are available
                                ":opensta_runfiles",
-                               ":vcd_{variant}_{stage}".format(variant = variant, stage = stage),
                                ":load_mock_array.tcl",
-                           ] + ["{macro}_{variant}_{stage}".format(
+                           ] + ([
+                               ":vcd_{variant}_{stage}".format(variant = variant, stage = stage),
+                           ] if needs_vcd else []) + ["{macro}_{variant}_{stage}".format(
                                variant = (name + "_base") if macro == "Element" else variant,
                                macro = macro,
                                stage = stage,
@@ -537,6 +632,27 @@ def mock_array(name, config):
                     ],
                 )
 
+        orfs_run(
+            name = "MockArray_{variant}_macro_layout".format(variant = variant),
+            src = ":MockArray_{variant}_floorplan".format(variant = variant),
+            outs = ["{variant}_macro_layout.txt".format(variant = variant)],
+            arguments = {
+                "ARRAY_COLS": str(config["cols"]),
+                "ARRAY_ROWS": str(config["rows"]),
+                "OUTPUT": "$(location :{variant}_macro_layout.txt)".format(variant = variant),
+            },
+            script = ":check_macro_layout.tcl",
+            tags = ["manual"],
+            visibility = ["//visibility:public"],
+        )
+
+        sh_test(
+            name = "MockArray_{variant}_macro_layout_test".format(variant = variant),
+            srcs = ["ok.sh"],
+            args = ["$(location :MockArray_{variant}_macro_layout)".format(variant = variant)],
+            data = [":MockArray_{variant}_macro_layout".format(variant = variant)],
+        )
+
         for power_test in ELEMENT_POWER_TESTS:
             if v != "base":
                 continue
diff --git a/test/orfs/mock-array/place_mock_array.tcl b/test/orfs/mock-array/place_mock_array.tcl
new file mode 100644
index 00000000000..ee7c4fc6d82
--- /dev/null
+++ b/test/orfs/mock-array/place_mock_array.tcl
@@ -0,0 +1,42 @@
+# Deterministic macro placement for the MockArray Element grid.
+#
+# Places ARRAY_ROWS x ARRAY_COLS Element macros (named
+# ces_row[r].ces_col[c].ces per MockArray.sv) on a regular grid with
+# row 0 at the bottom-left and indices increasing toward the upper right.
+# Rows are abutted in X (x_pitch = Element width); a small Y gap is left
+# for clock routing.
+
+set block [ord::get_db_block]
+set core [$block getCoreArea]
+
+set element [lindex [find_macros] 0]
+set bbox [$element getBBox]
+
+set x_pitch [$bbox getDX]
+set y_pitch [expr { [$bbox getDY] + 4 / [ord::dbu_to_microns 1] }]
+
+set rows $::env(ARRAY_ROWS)
+set cols $::env(ARRAY_COLS)
+
+set x_offset [expr {
+  [$core xMin] +
+  ([$core dx] - ($cols - 1) * $x_pitch - [$bbox getDX]) / 2
+}]
+set y_offset [expr {
+  [$core yMin] +
+  ([$core dy] - ($rows - 1) * $y_pitch - [$bbox getDY]) / 2
+}]
+
+for { set r 0 } { $r < $rows } { incr r } {
+  for { set c 0 } { $c < $cols } { incr c } {
+    # Instance names use backslash-escaped brackets in ODB (matching the
+    # Verilog escaped identifier form); use brace-quoted format literal.
+    set macro_name [format {ces_row\[%d\].ces_col\[%d\].ces} $r $c]
+    set x [expr { $c * $x_pitch + $x_offset }]
+    set y [expr { $r * $y_pitch + $y_offset }]
+    place_macro -macro_name $macro_name \
+      -location [list [expr { [ord::dbu_to_microns 1] * $x }] \
+        [expr { [ord::dbu_to_microns 1] * $y }]] \
+      -orientation R0
+  }
+}
diff --git a/test/orfs/mock-array/rules-4x4_base.json b/test/orfs/mock-array/rules-4x4_base.json
index e0e4eaff98c..0a5fcb8fe7d 100644
--- a/test/orfs/mock-array/rules-4x4_base.json
+++ b/test/orfs/mock-array/rules-4x4_base.json
@@ -1,8 +1,4 @@
 {
-    "synth__design__instance__area__stdcell": {
-        "value": 3550.0,
-        "compare": "<="
-    },
     "constraints__clocks__count": {
         "value": 1,
         "compare": "=="
@@ -99,4 +95,4 @@
         "value": 5728,
         "compare": "<="
     }
-}
\ No newline at end of file
+}
diff --git a/test/orfs/mock-array/rules-4x4_flat.json b/test/orfs/mock-array/rules-4x4_flat.json
index cb6c20499df..9cf0c77c867 100644
--- a/test/orfs/mock-array/rules-4x4_flat.json
+++ b/test/orfs/mock-array/rules-4x4_flat.json
@@ -1,8 +1,4 @@
 {
-    "synth__design__instance__area__stdcell": {
-        "value": 3550.0,
-        "compare": "<="
-    },
     "constraints__clocks__count": {
         "value": 1,
         "compare": "=="
@@ -99,4 +95,4 @@
         "value": 5728,
         "compare": "<="
     }
-}
\ No newline at end of file
+}
diff --git a/test/orfs/mock-array/rules-8x8_base.json b/test/orfs/mock-array/rules-8x8_base.json
index 941a6081f7a..09b934716be 100644
--- a/test/orfs/mock-array/rules-8x8_base.json
+++ b/test/orfs/mock-array/rules-8x8_base.json
@@ -1,8 +1,4 @@
 {
-    "synth__design__instance__area__stdcell": {
-        "value": 14100.0,
-        "compare": "<="
-    },
     "constraints__clocks__count": {
         "value": 1,
         "compare": "=="
@@ -99,4 +95,4 @@
         "value": 22491,
         "compare": "<="
     }
-}
\ No newline at end of file
+}
diff --git a/test/orfs/mock-array/rules-8x8_flat.json b/test/orfs/mock-array/rules-8x8_flat.json
index 941a6081f7a..09b934716be 100644
--- a/test/orfs/mock-array/rules-8x8_flat.json
+++ b/test/orfs/mock-array/rules-8x8_flat.json
@@ -1,8 +1,4 @@
 {
-    "synth__design__instance__area__stdcell": {
-        "value": 14100.0,
-        "compare": "<="
-    },
     "constraints__clocks__count": {
         "value": 1,
         "compare": "=="
@@ -99,4 +95,4 @@
         "value": 22491,
         "compare": "<="
     }
-}
\ No newline at end of file
+}
diff --git a/test/orfs/mock-array/simulate.cpp b/test/orfs/mock-array/simulate.cpp
index 1e97072d25a..83756f67eee 100644
--- a/test/orfs/mock-array/simulate.cpp
+++ b/test/orfs/mock-array/simulate.cpp
@@ -8,15 +8,26 @@
 
 std::vector<std::string_view> arguments(int argc, char* argv[])
 {
-  std::vector<std::string_view> x = {};
+  std::vector<std::string_view> filtered_args = {};
   for (int i = 1; i < argc; ++i) {
     auto arg = std::string_view(argv[i]);
     if (arg.starts_with("+verilator")) {
       continue;
     }
-    x.push_back(arg);
+    filtered_args.push_back(arg);
   }
-  return x;
+  return filtered_args;
+}
+
+// Write a 64-bit value into a specific 64-bit slot of a wide bus.
+// Yosys flattens unpacked arrays into wide packed buses, so
+// io_ins_down[N] becomes io_ins_down[N*64-1:0] with element i at
+// bits [i*64+63 : i*64].
+static void write_slot(WData* bus, int slot, QData value)
+{
+  int word = slot * 2;  // 64 bits = 2 x 32-bit words
+  bus[word] = static_cast<IData>(value);
+  bus[word + 1] = static_cast<IData>(value >> 32);
 }
 
 int main(int argc, char** argv)
@@ -37,29 +48,39 @@ int main(int argc, char** argv)
   top->reset = 1;
   top->clock = 0;
 
-  // There's no great way to do this, we need to
-  // refer to static names from Verilator generated code,
-  // inject them on the command line.
-  QData* inputs[] = {ARRAY_COLS, ARRAY_ROWS};
-
   top->trace(vcd, 99);  // Trace all levels of hierarchy
   vcd->open(args.front().data());
 
   int tick = 0;
-  for (auto input : inputs) {
-    for (int i = 0; i < 5; i++) {
-      if (Verilated::gotFinish()) {
-        goto done;
-      }
-      *input = tick ^ ((tick / 2) % 2 ? 0 : 0xffffffffffffffffUL);
-      if (tick == 9) {
-        top->reset = 0;
-      }
 
-      for (int k = 0; k < 2; k++) {
-        top->eval();
-        vcd->dump(tick++ * 125);
-        top->clock = !top->clock;
+  // Stimulate column buses (down/up), then row buses (left/right)
+  struct
+  {
+    WData* bus1;
+    WData* bus2;
+    int count;
+  } stimuli[] = {
+      {top->io_ins_down.data(), top->io_ins_up.data(), ARRAY_COLS},
+      {top->io_ins_left.data(), top->io_ins_right.data(), ARRAY_ROWS},
+  };
+
+  for (auto& s : stimuli) {
+    for (int idx = 0; idx < s.count; idx++) {
+      for (int i = 0; i < 5; i++) {
+        if (Verilated::gotFinish()) {
+          goto done;
+        }
+        QData value = tick ^ ((tick / 2) % 2 ? 0 : 0xffffffffffffffffUL);
+        write_slot(s.bus1, idx, value);
+        write_slot(s.bus2, idx, value);
+        if (tick == 9) {
+          top->reset = 0;
+        }
+        for (int k = 0; k < 2; k++) {
+          top->eval();
+          vcd->dump(tick++ * 125);
+          top->clock = !top->clock;
+        }
       }
     }
   }
@@ -68,6 +89,7 @@ int main(int argc, char** argv)
   vcd->close();
 
   top->final();
+  delete vcd;
   delete top;
   return 0;
 }
diff --git a/test/orfs/mock-array/src/main/scala/MockArray.scala b/test/orfs/mock-array/src/main/scala/MockArray.scala
deleted file mode 100644
index 74aa38b56b9..00000000000
--- a/test/orfs/mock-array/src/main/scala/MockArray.scala
+++ /dev/null
@@ -1,246 +0,0 @@
-// to generate code, run:
-// ../../asap7/mock-array/configure.sh
-
-import circt.stage.ChiselStage
-import chisel3._
-import chisel3.util._
-import chisel3.stage._
-import chisel3.experimental._
-import chisel3.util.HasBlackBoxResource
-import scopt.OParser
-import System.err
-import scopt.RenderingMode
-import scala.collection.immutable.SeqMap
-import java.nio.file.Paths
-
-object Routes extends Enumeration {
-  type Routes = Value
-
-  val LEFT, UP, RIGHT, DOWN = Value
-}
-
-class RoutesVec(singleElementWidth: Int) extends Record {
-  val routes = SeqMap(Routes.values.toSeq.map { bus =>
-    bus -> UInt(singleElementWidth.W)
-  }: _*)
-  val elements = routes.map { case (a, b) => a.toString().toLowerCase() -> b }
-
-  def asMap: SeqMap[Routes.Value, UInt] = routes
-  def asSeq: Seq[UInt] = routes.map(_._2).toSeq
-}
-
-class BusesVec(singleElementWidth: Int, width: Int, height: Int)
-    extends Record {
-  val routes = SeqMap(
-    Routes.LEFT -> Vec(height, UInt(singleElementWidth.W)),
-    Routes.RIGHT -> Vec(height, UInt(singleElementWidth.W)),
-    Routes.UP -> Vec(width, UInt(singleElementWidth.W)),
-    Routes.DOWN -> Vec(width, UInt(singleElementWidth.W))
-  )
-  val elements = routes.map { case (a, b) => a.toString().toLowerCase() -> b }
-
-  def asMap: SeqMap[Routes.Value, Vec[UInt]] = routes
-  def asSeq: Seq[Vec[UInt]] = routes.map(_._2).toSeq
-}
-
-class MockArrayBundle(width: Int, height: Int, singleElementWidth: Int)
-    extends Bundle {
-  val ins = Input(new BusesVec(singleElementWidth, width, height))
-  val outs = Output(new BusesVec(singleElementWidth, width, height))
-  val lsbs = Output(Vec(width * height, Bool()))
-}
-
-class MultiplierIO extends Bundle {
-  val a = Input(UInt(32.W))
-  val b = Input(UInt(32.W))
-  val o = Output(UInt(32.W))
-  val rst = Input(Bool())
-  val clk = Input(Clock())
-}
-
-// Generated with:
-//
-// vlsi-multiplier --register-input --register-post-ppg --register-post-ppa --register-output --bits=32 --algorithm=brentkung --tech=asap7 --output=multiplier.v
-class MultiplierBlackBox extends BlackBox with HasBlackBoxResource {
-  override def desiredName = "multiplier"
-  val io = IO(new MultiplierIO())
-}
-
-// This module is kept in synthesis for hierarchical power testing purposes
-class Multiplier extends RawModule {
-  val io = IO(new MultiplierIO())
-
-  val mod = Module(new MultiplierBlackBox())
-  mod.io.a := io.a
-  mod.io.b := io.b
-  mod.io.rst := io.rst
-  mod.io.clk := io.clk
-  // reduce output bit-width until we slight negative slack
-  // and also until we run in a few minutes for fast local
-  // smoke-testing
-  io.o := mod.io.o(3, 0)
-}
-
-class MockArray(width: Int, height: Int, singleElementWidth: Int)
-    extends Module {
-  val io = IO(new MockArrayBundle(width, height, singleElementWidth))
-
-  class Element extends Module {
-    val io =
-      IO(new Bundle {
-        val ins = Input(new RoutesVec(singleElementWidth))
-        val outs = Output(new RoutesVec(singleElementWidth))
-
-        val lsbIns = Input(Vec(width, Bool()))
-        val lsbOuts = Output(Vec(width, Bool()))
-      })
-
-    // Registered routing paths
-    //  left <-> down
-    //  up <-> right
-    (io.outs.asSeq zip (io.ins.asSeq ++ Seq(io.ins.asSeq.head))
-      .sliding(2)
-      .toSeq
-      .reverse
-      .map(_.map(RegNext(_)))).foreach { case (a, b) =>
-      a := RegNext({
-        val mult = Module(new Multiplier())
-        mult.io.a := b(0)
-        mult.io.b := b(1)
-        // save some area and complexity by not having reset
-        mult.io.rst := false.B
-        mult.io.clk := clock
-        mult.io.o
-      })
-    }
-
-    // Combinational logic, but a maximum flight path of number of
-    // elements horizontally / 2
-    val MAX_FLIGHT = width / 2
-    io.lsbOuts := (io.lsbIns
-      .drop(1)
-      .reverse
-      .sliding(MAX_FLIGHT, MAX_FLIGHT)
-      .map { lsbs =>
-        if (lsbs.length < MAX_FLIGHT) {
-          lsbs
-        } else {
-          lsbs.dropRight(1) ++ Seq(RegNext(lsbs.last))
-        }
-      })
-      .flatten
-      .toSeq
-      .reverse ++ Seq(io.outs.asSeq.head(0)(0))
-  }
-
-  val ces = Seq.fill(height)(Seq.fill(width)(Module(new Element())))
-
-  ces.foreach { row =>
-    row.head.io.lsbIns := DontCare
-    if (row.length > 1) {
-      row.sliding(2, 1).foreach { pair =>
-        pair(1).io.lsbIns := pair(0).io.lsbOuts
-      }
-    }
-  }
-
-  io.lsbs := RegNext(VecInit(ces.map(_.last.io.lsbOuts).flatten))
-
-  // Connect inputs to edge element buses
-  (ces.map(_.head).map(_.io.ins.asMap(Routes.RIGHT)) zip io.ins.asMap(
-    Routes.RIGHT
-  )).foreach { case (a, b) => a := b }
-  (ces.last.map(_.io.ins.asMap(Routes.DOWN)) zip io.ins.asMap(Routes.DOWN))
-    .foreach { case (a, b) => a := b }
-  (ces.map(_.last).map(_.io.ins.asMap(Routes.LEFT)) zip io.ins.asMap(
-    Routes.LEFT
-  )).foreach { case (a, b) => a := b }
-  (ces.head.map(_.io.ins.asMap(Routes.UP)) zip io.ins.asMap(Routes.UP))
-    .foreach { case (a, b) => a := b }
-
-  // Connect edge element buses to outputs
-  (ces.map(_.head).map(_.io.outs.asMap(Routes.LEFT)) zip io.outs.asMap(
-    Routes.LEFT
-  )).foreach { case (a, b) => b := a }
-  (ces.last.map(_.io.outs.asMap(Routes.UP)) zip io.outs.asMap(Routes.UP))
-    .foreach { case (a, b) => b := a }
-  (ces.map(_.last).map(_.io.outs.asMap(Routes.RIGHT)) zip io.outs.asMap(
-    Routes.RIGHT
-  )).foreach { case (a, b) => b := a }
-  (ces.head.map(_.io.outs.asMap(Routes.DOWN)) zip io.outs.asMap(Routes.DOWN))
-    .foreach { case (a, b) => b := a }
-
-  // Connect neighboring left/right element buses
-  (ces.transpose.flatten zip ces.transpose.drop(1).flatten).foreach {
-    case (a, b) =>
-      a.io.ins.asMap(Routes.LEFT) := b.io.outs.asMap(Routes.LEFT)
-      b.io.ins.asMap(Routes.RIGHT) := a.io.outs.asMap(Routes.RIGHT)
-  }
-
-  // Connect neighboring up/down element buses
-  (ces.flatten zip ces.drop(1).flatten).foreach { case (a, b) =>
-    a.io.ins.asMap(Routes.DOWN) := b.io.outs.asMap(Routes.DOWN)
-    b.io.ins.asMap(Routes.UP) := a.io.outs.asMap(Routes.UP)
-  }
-}
-
-case class ArrayConfig(
-    width: Int = 8,
-    height: Int = 8,
-    dataWidth: Int = 8,
-    remainingArgs: Seq[String] = Seq.empty
-)
-
-object parse {
-  def apply(
-      args: Array[String]
-  ): (ArrayConfig, Array[String], Array[String]) = {
-    val builder = OParser.builder[ArrayConfig]
-    val parser = {
-      import builder._
-      OParser.sequence(
-        programName("my-program"),
-        opt[Int]('w', "width")
-          .required()
-          .valueName("Array width")
-          .action((width, c) => c.copy(width = width))
-          .text("input file is required"),
-        opt[Int]('h', "height")
-          .required()
-          .valueName("height")
-          .action((height, c) => c.copy(height = height))
-          .text("Array height"),
-        opt[Int]('d', "dataWidth")
-          .required()
-          .valueName("dataWidth")
-          .action((dataWidth, c) => c.copy(dataWidth = dataWidth))
-          .text("data path width")
-      )
-    }
-
-    val (configArgs, firstDelimiter) = args.span(_ != "--")
-    val (chiselArgs, secondDelimiter) = firstDelimiter.drop(1).span(_ != "--")
-    val firtoolArgs = secondDelimiter.drop(1)
-
-    OParser.parse(parser, configArgs, ArrayConfig()) match {
-      case Some(c) =>
-        return (c, chiselArgs, firtoolArgs)
-
-      case _ =>
-        // arguments are invalid
-        OParser.usage(parser, RenderingMode.TwoColumns)
-        sys.exit(1)
-    }
-  }
-
-}
-
-object GenerateMockArray extends App {
-  val (c, chiselArgs, firtoolArgs) = parse(args)
-
-  ChiselStage.emitHWDialect(
-    new MockArray(c.width, c.height, c.dataWidth),
-    chiselArgs,
-    firtoolArgs
-  )
-}