dpl: modify default algorithm to negotiation legalizer

src/cts/test/buffer_ports.ok

@@ -50,26 +50,32 @@ Using 2 tracks default min distance between IO pins.
 [InitialPlace]  Iter: 3 conjugate gradient residual: 0.00000011 HPWL: 2164788
 [InitialPlace]  Iter: 4 conjugate gradient residual: 0.00000010 HPWL: 1701248
 [InitialPlace]  Iter: 5 conjugate gradient residual: 0.00000007 HPWL: 1688200
+[INFO DPL-0388] Cell height distribution (1 unique micron height(s)):
+[INFO DPL-0389]   height 1.400 um: 81 cells
 [INFO DPL-0006] Core area: 999570.01 um^2, Instances area: 121.56 um^2, Utilization: 0.0%
+[INFO DPL-0007] All instances area (incl. macros/pads/fixed): 121.56 um^2, Utilization: 0.0%
 [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically.
-[INFO DPL-1101] Legalizing using diamond search.
-Movements Summary
----------------------------------------
-Total cells:                      81
-Diamond Move Success:             81 (100.00%)
-Diamond Move Failure:              0
-Rip-up and replace Success:        0 (  0.00% of diamond failures)
-Rip-up and replace Failure:        0
-Total Placement Failures:          0
----------------------------------------
+[INFO DPL-1102] Legalizing using negotiation legalizer.
+[INFO DPL-1103] NegotiationLegalizer search window: +/-20 sites horizontally, +/-5 rows vertically.
+[INFO DPL-1104] NegotiationLegalizer DRC penalty: 5.
+[INFO DPL-0392] Negotiation cell height distribution (1 unique row-count(s)):
+[INFO DPL-0393]   height 1 row(s): 81 cells
+          |      Total |  Illegal |  Illegal
+Iteration | Violations |    Cells |    Sites
+---------------------------------------------
+        0 |       1081 |        71 |       328
+        1 |        203 |        31 |       127
+        2 |         12 |         4 |         8
+        3 |          0 |         0 |         0
+Negotiation phase 1 converged at iteration 3.
 Placement Analysis
 ---------------------------------
-total displacement        798.6 u
-average displacement        9.9 u
-max displacement           13.0 u
+total displacement          0.0 u
+average displacement        0.0 u
+max displacement            0.0 u
 original HPWL             573.2 u
-legalized HPWL           1628.1 u
-delta HPWL                  184 %
+legalized HPWL           1545.2 u
+delta HPWL                  170 %
 
 [INFO CTS-0050] Root buffer is BUF_X1.
 [INFO CTS-0051] Sink buffer is BUF_X1.
@@ -88,14 +94,14 @@ delta HPWL                  184 %
 [INFO CTS-0030]  Number of static layers: 1.
 [INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
 [INFO CTS-0021]  Distance between buffers: 7 units (100 um).
-[INFO CTS-0023]  Original sink region: [(3230, 1230), (10890, 18025)].
-[INFO CTS-0024]  Normalized sink region: [(0.230714, 0.0878571), (0.777857, 1.2875)].
-[INFO CTS-0025]     Width:  0.5471.
-[INFO CTS-0026]     Height: 1.1996.
+[INFO CTS-0023]  Original sink region: [(250, 12430), (11210, 43570)].
+[INFO CTS-0024]  Normalized sink region: [(0.0178571, 0.887857), (0.800714, 3.11214)].
+[INFO CTS-0025]     Width:  0.7829.
+[INFO CTS-0026]     Height: 2.2243.
  Level 1
     Direction: Vertical
     Sinks per sub-region: 5
-    Sub-region size: 0.5471 X 0.5998
+    Sub-region size: 0.7829 X 1.1121
 [INFO CTS-0034]     Segment length (rounded): 1.
 [INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
 [INFO CTS-0035]  Number of sinks covered: 9.
@@ -108,6 +114,6 @@ delta HPWL                  184 %
 [INFO CTS-0098] Clock net "clk"
 [INFO CTS-0099]  Sinks 10
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 506.70 um
+[INFO CTS-0101]  Average sink wire length 494.61 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Dummy loads inserted 1