Skip to content

cts: isolate tests from global and detailed placement (#10749) #10769

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
maliberty merged 1 commit into from
Jun 30, 2026
Merged

cts: isolate tests from global and detailed placement (#10749) #10769

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1,013 changes: 1,013 additions & 0 deletions src/cts/test/buffer_ports.def
View file
Open in desktop

Large diffs are not rendered by default.

76 changes: 4 additions & 72 deletions src/cts/test/buffer_ports.ok
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,76 +1,8 @@
[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
[INFO IFP-0001] Added 714 rows of 5263 site FreePDK45_38x28_10R_NP_162NW_34O.
[INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 1000.000 1000.000 ) um
[INFO IFP-0101] Core BBox: ( 0.000 0.000 ) ( 999.970 999.600 ) um
[INFO IFP-0102] Core area: 999570.012 um^2
[INFO IFP-0103] Total instances area: 111.454 um^2
[INFO IFP-0104] Effective utilization: 0.000
[INFO IFP-0105] Number of instances: 68
[INFO RSZ-0026] Removed 5 buffers.
[INFO RSZ-0027] Inserted 9 BUF_X1 input buffers.
[INFO RSZ-0028] Inserted 9 BUF_X1 output buffers.
Found 0 macro blocks.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0001] Number of available slots 12380
[INFO PPL-0002] Number of I/O 19
[INFO PPL-0003] Number of I/O w/sink 19
[INFO PPL-0004] Number of I/O w/o sink 0
[INFO PPL-0005] Slots per section 200
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 1057.01 um.
[INFO GPL-0001] ---- Initialize GPL Main Data Structures
[INFO GPL-0002] DBU: 2000
[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um
[INFO GPL-0004] CoreBBox: ( 0.000 0.000 ) ( 999.970 999.600 ) um
[INFO GPL-0036] Movable instances area: 121.562 um^2
[INFO GPL-0037] Total instances area: 121.562 um^2
[INFO GPL-0035] Pin density area adjust: 7.987 um^2
[INFO GPL-0032] ---- Initialize Region: Top-level
[INFO GPL-0006] Number of instances: 81
[INFO GPL-0007] Movable instances: 81
[INFO GPL-0008] Fixed instances: 0
[INFO GPL-0009] Dummy instances: 0
[INFO GPL-0010] Number of nets: 107
[INFO GPL-0011] Number of pins: 281
[INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 1000.000 1000.000 ) um
[INFO GPL-0013] Core BBox: ( 0.000 0.000 ) ( 999.970 999.600 ) um
[INFO GPL-0016] Core area: 999570.012 um^2
[INFO GPL-0014] Region name: top-level.
[INFO GPL-0015] Region area: 999570.012 um^2
[INFO GPL-0017] Fixed instances area: 0.000 um^2
[INFO GPL-0018] Movable instances area: 129.549 um^2
[INFO GPL-0019] Utilization: 0.013 %
[INFO GPL-0020] Standard cells area: 129.549 um^2
[INFO GPL-0021] Large instances area: 0.000 um^2
[INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement.
[INFO GPL-0051] Source of initial instance position counters:
Odb location = 18 Core center = 63 Region center = 0
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000006 HPWL: 1722700
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000005 HPWL: 8121024
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000011 HPWL: 2164788
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000010 HPWL: 1701248
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000007 HPWL: 1688200
[INFO DPL-0006] Core area: 999570.01 um^2, Instances area: 121.56 um^2, Utilization: 0.0%
[INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically.
[INFO DPL-1101] Legalizing using diamond search.
Movements Summary
---------------------------------------
Total cells: 81
Diamond Move Success: 81 (100.00%)
Diamond Move Failure: 0
Rip-up and replace Success: 0 ( 0.00% of diamond failures)
Rip-up and replace Failure: 0
Total Placement Failures: 0
---------------------------------------
Placement Analysis
---------------------------------
total displacement 798.6 u
average displacement 9.9 u
max displacement 13.0 u
original HPWL 573.2 u
legalized HPWL 1628.1 u
delta HPWL 184 %

[INFO ODB-0128] Design: clk_passthrough_top
[INFO ODB-0130] Created 19 pins.
[INFO ODB-0131] Created 81 components and 424 component-terminals.
[INFO ODB-0133] Created 107 nets and 262 connections.
[INFO CTS-0050] Root buffer is BUF_X1.
[INFO CTS-0051] Sink buffer is BUF_X1.
[INFO CTS-0052] The following clock buffers will be used for CTS:
Expand Down
19 changes: 2 additions & 17 deletions src/cts/test/buffer_ports.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,27 +1,12 @@
# Test CTS design with input/output port buffers on passthrough top design
source "helpers.tcl"

source Nangate45/Nangate45.vars
read_liberty Nangate45/Nangate45_typ.lib
read_lef Nangate45/Nangate45.lef
read_verilog buffer_ports.v

link_design clk_passthrough_top

read_def buffer_ports.def
read_sdc buffer_ports.sdc

@maliberty maliberty Jun 27, 2026

Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

you should still read the sdc

@s-sreedhar s-sreedhar Jun 28, 2026

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Ok i have rectified


initialize_floorplan -die_area "0 0 1000 1000" -core_area "0 0 1000 1000" \
-site FreePDK45_38x28_10R_NP_162NW_34O
#make_io_sites -horizontal_site IOSITE -vertical_site IOSITE -corner_site IOSITE -offset 15
source $tracks_file

remove_buffers
buffer_ports

place_pins -hor_layers $io_placer_hor_layer \
-ver_layers $io_placer_ver_layer
global_placement -skip_nesterov_place
detailed_placement


source Nangate45/Nangate45.rc
source $layer_rc_file
Expand Down
Loading
Loading