est: add multi-tech/chip wire RC support

[eder-matheus]

Summary

Multi-tech / per-chip wire RC support for parasitics estimation, building on #10931.

Re-keys the layer RC table by dbTechLayer* instead of layer->getNumber(), moves wire RC values and signal/clock layer lists into a per-chip container (dbChip*-keyed, with a default slot preserving 2D behavior), and adds chip selectors to set_wire_rc:

• -tech <name> (all chips on that technology)
• -chip <name>
• -redistribution_layer (all RDL chips; warns and no-ops when the design has none, so shared scripts work across designs).

Layer lookups for -layer/-layers resolve in the targeted chip's technology.
The multi-chip consumer of these values, the per-chip estimation loop, follows in a separate PR

Type of Change

• New feature

Impact

2D flows are unchanged (values land in the default slot; est regression results are identical). In 3D databases, wire RC can now be set per chip/technology, which the upcoming per-chip estimation flow consumes.
Selector errors: unknown -chip name and mutually exclusive selectors are hard errors; -tech/-redistribution_layer matching no chips warn and are ignored.

Verification

• I have verified that the local build succeeds (./etc/Build.sh).
• I have run the relevant tests and they pass.
• My code follows the repository's formatting guidelines.
• I have included tests to prevent regressions.
• I have signed my commits (DCO).

Related Issues

Follow-up to #10931.

[eder-matheus]

@codex review

[gemini-code-assist]

Code Review

This pull request introduces support for storing and resolving wire resistance and capacitance (RC) values per chip to support 3D designs. It updates the TCL interface for set_wire_rc with new chip selectors (-tech, -chip, and -redistribution_layer), maps wire RC configurations by odb::dbChip* in the C++ backend, and adds corresponding unit tests. The review feedback highlights a redundant and potentially unsafe initialization of db_cbk_ in the constructor, a redundant map lookup and potential out-of-bounds access in layerRC, and a double lookup optimization opportunity in findWireRC when the current chip is null.

[chatgpt-codex-connector]

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