est: add multi-tech/chip wire RC support

src/est/README.md

@@ -15,6 +15,9 @@ The `set_wire_rc` command sets the resistance and capacitance used to estimate
 delay of routing wires.  Separate values can be specified for clock and data
 nets with the `-signal` and `-clock` flags. Without either `-signal` or
 `-clock` the resistance and capacitance for clocks and data nets are set.
+In 3D designs the values can be targeted at specific chips with the `-tech`,
+`-chip` and `-redistribution_layer` selectors; without a selector the values
+are the defaults used by chips that have no chip-specific values.
 
 ```
 # Either run 
@@ -31,13 +34,19 @@ set_wire_rc
     [-data]
     [-corner corner]
     [-layers layers_list]
+    [-tech tech]
+    [-chip chip]
+    [-redistribution_layer]
 
 or 
 set_wire_rc
     [-h_resistance res]
     [-h_capacitance cap]
     [-v_resistance res]
     [-v_capacitance cap]
+    [-tech tech]
+    [-chip chip]
+    [-redistribution_layer]
 
 or
 set_wire_rc 
@@ -46,10 +55,16 @@ set_wire_rc
     [-data]
     [-corner corner]
     [-layer layer_name]
+    [-tech tech]
+    [-chip chip]
+    [-redistribution_layer]
 or 
 set_wire_rc
     [-resistance res]
     [-capacitance cap]
+    [-tech tech]
+    [-chip chip]
+    [-redistribution_layer]
 ```
 
 #### Options
@@ -66,6 +81,14 @@ set_wire_rc
 | `-h_capacitance` | Capacitance per unit length for horizontal wires, units are from the first Liberty file read. |
 | `-v_resistance` | Resistance per unit length for vertical wires, units are from the first Liberty file read. |
 | `-v_capacitance` | Capacitance per unit length for vertical wires, units are from the first Liberty file read. |
+| `-tech` | Apply the values to all chips using this technology (3D designs). Layers given with `-layer`/`-layers` are looked up in this technology. |
+| `-chip` | Apply the values to the named chip only (3D designs). |
+| `-redistribution_layer` | Apply the values to every RDL chip in the design, however many there are. Warns and does nothing when the design has none, so shared scripts work across designs. `-layer`/`-layers` require the selected RDL chips to share one technology; with mixed RDL technologies set each chip separately with `-chip`. |
+
+Without `-tech`, `-chip` or `-redistribution_layer` the values are the defaults
+used by every chip that has no chip-specific values. Signal values, clock
+values and routing layers fall back to the defaults independently, so a chip
+with only chip-specific signal values still uses the default clock values.
 
 ### Set Layer RC
 

src/est/include/est/EstimateParasitics.h

@@ -12,6 +12,7 @@
 #include <ostream>
 #include <set>
 #include <string>
+#include <unordered_map>
 #include <unordered_set>
 #include <vector>
 
@@ -99,25 +100,31 @@ class EstimateParasitics : public sta::dbStaState, public ParasiticsService
                // Return values.
                double& res,
                double& cap) const;
-  void addClkLayer(odb::dbTechLayer* layer);
-  void addSignalLayer(odb::dbTechLayer* layer);
+  // A null chip in the setters below writes the default values used by
+  // chips without chip-specific values.
+  void addClkLayer(odb::dbChip* chip, odb::dbTechLayer* layer);
+  void addSignalLayer(odb::dbChip* chip, odb::dbTechLayer* layer);
   void sortClkAndSignalLayers();
   // Set the resistance and capacitance used for horizontal parasitics on signal
   // nets.
-  void setHWireSignalRC(const sta::Scene* scene,
+  void setHWireSignalRC(odb::dbChip* chip,
+                        const sta::Scene* scene,
                         double res,   // ohms/meter
                         double cap);  // farads/meter
   // Set the resistance and capacitance used for vertical wires parasitics on
   // signal nets.
-  void setVWireSignalRC(const sta::Scene* scene,
+  void setVWireSignalRC(odb::dbChip* chip,
+                        const sta::Scene* scene,
                         double res,   // ohms/meter
                         double cap);  // farads/meter
   // Set the resistance and capacitance used for parasitics on clock nets.
-  void setHWireClkRC(const sta::Scene* scene,
+  void setHWireClkRC(odb::dbChip* chip,
+                     const sta::Scene* scene,
                      double res,
                      double cap);  // farads/meter
   // Set the resistance and capacitance used for parasitics on clock nets.
-  void setVWireClkRC(const sta::Scene* scene,
+  void setVWireClkRC(odb::dbChip* chip,
+                     const sta::Scene* scene,
                      double res,
                      double cap);  // farads/meter
   // ohms/meter, farads/meter
@@ -210,6 +217,23 @@ class EstimateParasitics : public sta::dbStaState, public ParasiticsService
   utl::Logger* getLogger() { return logger_; }
 
  private:
+  // Wire RC values and layers of one chip, indexed by corner->index()
+  struct WireRC
+  {
+    std::vector<odb::dbTechLayer*> signal_layers;
+    std::vector<odb::dbTechLayer*> clk_layers;
+    std::vector<ParasiticsResistance> signal_res;   // ohms/meter
+    std::vector<ParasiticsCapacitance> signal_cap;  // Farads/meter
+    std::vector<ParasiticsResistance> clk_res;      // ohms/meter
+    std::vector<ParasiticsCapacitance> clk_cap;     // Farads/meter
+  };
+
+  odb::dbChip* currentChip() const;
+  WireRC& wireRC(odb::dbChip* chip) { return wire_rc_[chip]; }
+  // Resolve one WireRC category for the current chip; a category left unset
+  // for a chip falls back to the defaults (nullptr entry) independently.
+  template <typename T>
+  const std::vector<T>& resolveWireRC(std::vector<T> WireRC::*category) const;
   void ensureParasitics();
   bool isIdealClockPin(const sta::Pin* pin) const;
   bool isIdealClockNet(const sta::Net* net) const;
@@ -258,17 +282,14 @@ class EstimateParasitics : public sta::dbStaState, public ParasiticsService
   odb::dbBlock* block_ = nullptr;
   std::unique_ptr<OdbCallBack> db_cbk_;
 
-  std::vector<odb::dbTechLayer*> signal_layers_;
-  std::vector<odb::dbTechLayer*> clk_layers_;
-  // Layer RC per wire length indexed by layer->getNumber(), corner->index
-  std::vector<std::vector<double>> layer_res_;  // ohms/meter
-  std::vector<std::vector<double>> layer_cap_;  // Farads/meter
-  // Signal wire RC indexed by corner->index
-  std::vector<ParasiticsResistance> wire_signal_res_;   // ohms/metre
-  std::vector<ParasiticsCapacitance> wire_signal_cap_;  // Farads/meter
-  // Clock wire RC.
-  std::vector<ParasiticsResistance> wire_clk_res_;   // ohms/metre
-  std::vector<ParasiticsCapacitance> wire_clk_cap_;  // Farads/meter
+  // Layer RC per wire length keyed by layer, indexed by corner->index()
+  std::unordered_map<odb::dbTechLayer*, std::vector<double>>
+      layer_res_;  // ohms/meter
+  std::unordered_map<odb::dbTechLayer*, std::vector<double>>
+      layer_cap_;  // Farads/meter
+  // Wire RC per chip; the nullptr entry holds the defaults used by chips
+  // without chip-specific values
+  std::unordered_map<odb::dbChip*, WireRC> wire_rc_;
 
   ParasiticsSrc parasitics_src_ = ParasiticsSrc::kNone;