diff --git a/src/ram/include/ram/ram.h b/src/ram/include/ram/ram.h index f75acf44526..17d83c38914 100644 --- a/src/ram/include/ram/ram.h +++ b/src/ram/include/ram/ram.h @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -50,6 +51,29 @@ class TritonRoute; namespace ram { +enum class PortRoleType +{ + Clock, + DataIn, + DataOut, + WriteEnable, + TriEnable, + Select, // for mux support in future + Power, + Ground +}; + +struct PortRole +{ + PortRoleType type; + int index; + +// for map so that keys are comparable +#ifndef SWIG + auto operator<=>(const PortRole&) const = default; +#endif +}; + class RamGen { public: @@ -96,15 +120,10 @@ class RamGen private: void findMasters(); + std::map buildPortMap(odb::dbMaster*); odb::dbMaster* findMaster(const std::function& match, const char* name); odb::dbNet* makeNet(const std::string& prefix, const std::string& name); - odb::dbInst* makeInst( - Layout* layout, - const std::string& prefix, - const std::string& name, - odb::dbMaster* master, - const std::vector>& connections); odb::dbInst* makeInst( Cell* cell, const std::string& prefix, @@ -168,6 +187,13 @@ class RamGen odb::dbMaster* buffer_cell_{nullptr}; odb::dbMaster* tapcell_{nullptr}; + std::map storage_ports_; + std::map tristate_ports_; + std::map inv_ports_; + std::map and2_ports_; + std::map clock_gate_ports_; + std::map buffer_ports_; + std::vector addr_inputs_; std::vector data_inputs_; std::vector> q_outputs_; diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index 8b521759f47..43b4d441f46 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -120,18 +121,20 @@ std::unique_ptr RamGen::makeBit(const std::string& prefix, prefix, "bit", storage_cell_, - {{storage_cell_->findMTerm("CLK") ? "CLK" : "GATE", clock}, - {"D", data_input}, - {"Q", storage_net}}); + {{storage_ports_[{PortRoleType::Clock, 0}], clock}, + {storage_ports_[{PortRoleType::DataIn, 0}], data_input}, + {storage_ports_[{PortRoleType::DataOut, 0}], storage_net}}); for (int read_port = 0; read_port < read_ports; ++read_port) { - makeInst(bit_cell.get(), - prefix, - fmt::format("obuf{}", read_port), - tristate_cell_, - {{"A", storage_net}, - {"TE_B", select[read_port]}, - {"Z", data_output[read_port]}}); + makeInst( + bit_cell.get(), + prefix, + fmt::format("obuf{}", read_port), + tristate_cell_, + {{tristate_ports_[{PortRoleType::DataIn, 0}], storage_net}, + {tristate_ports_[{PortRoleType::TriEnable, 0}], select[read_port]}, + {tristate_ports_[{PortRoleType::DataOut, 0}], + data_output[read_port]}}); } return bit_cell; @@ -178,7 +181,9 @@ void RamGen::makeSlice(const int slice_idx, prefix, "cg", clock_gate_cell_, - {{"CLK", clock}, {"GATE", we0_net}, {"GCLK", gclock_net}}); + {{clock_gate_ports_[{PortRoleType::Clock, 0}], clock}, + {clock_gate_ports_[{PortRoleType::DataIn, 0}], we0_net}, + {clock_gate_ports_[{PortRoleType::DataOut, 0}], gclock_net}}); // Make clock and // this AND gate needs to be fed a net created by a decoder @@ -187,7 +192,9 @@ void RamGen::makeSlice(const int slice_idx, prefix, "gcand", and2_cell_, - {{"A", selects[0]}, {"B", write_enable}, {"X", we0_net}}); + {{and2_ports_[{PortRoleType::DataIn, 0}], selects[0]}, + {and2_ports_[{PortRoleType::DataIn, 1}], write_enable}, + {and2_ports_[{PortRoleType::DataOut, 0}], we0_net}}); // Make select inverters for (int i = 0; i < selects.size(); ++i) { @@ -195,7 +202,8 @@ void RamGen::makeSlice(const int slice_idx, prefix, fmt::format("select_inv_{}", i), inv_cell_, - {{"A", selects[i]}, {"Y", select_b_nets[i]}}); + {{inv_ports_[{PortRoleType::DataIn, 0}], selects[i]}, + {inv_ports_[{PortRoleType::DataOut, 0}], select_b_nets[i]}}); } ram_grid_.addCell(std::move(sel_cell), start_bit_idx + mask_size + slice_idx); @@ -278,30 +286,36 @@ std::unique_ptr RamGen::makeDecoder( prefix, fmt::format("and_layer{}", i), and2_cell_, - {{"A", addr_nets[i]}, - {"B", addr_nets[i + 1]}, - {"X", decoder_out_net}}); + {{and2_ports_[{PortRoleType::DataIn, 0}], addr_nets[i]}, + {and2_ports_[{PortRoleType::DataIn, 1}], addr_nets[i + 1]}, + {and2_ports_[{PortRoleType::DataOut, 0}], decoder_out_net}}); prev_net = input_net; } else if (i == 0) { makeInst(word_cell.get(), prefix, fmt::format("and_layer{}", i), and2_cell_, - {{"A", addr_nets[i]}, {"B", input_net}, {"X", decoder_out_net}}); + {{and2_ports_[{PortRoleType::DataIn, 0}], addr_nets[i]}, + {and2_ports_[{PortRoleType::DataIn, 1}], input_net}, + {and2_ports_[{PortRoleType::DataOut, 0}], decoder_out_net}}); prev_net = input_net; } else if (i == layers - 1) { // last AND gate layer makeInst(word_cell.get(), prefix, fmt::format("and_layer{}", i), and2_cell_, - {{"A", addr_nets[i]}, {"B", addr_nets[i + 1]}, {"X", prev_net}}); + {{and2_ports_[{PortRoleType::DataIn, 0}], addr_nets[i]}, + {and2_ports_[{PortRoleType::DataIn, 1}], addr_nets[i + 1]}, + {and2_ports_[{PortRoleType::DataOut, 0}], prev_net}}); prev_net = input_net; } else { // middle AND gate layers makeInst(word_cell.get(), prefix, fmt::format("and_layer{}", i), and2_cell_, - {{"A", addr_nets[i]}, {"B", input_net}, {"X", prev_net}}); + {{and2_ports_[{PortRoleType::DataIn, 0}], addr_nets[i]}, + {and2_ports_[{PortRoleType::DataIn, 1}], input_net}, + {and2_ports_[{PortRoleType::DataOut, 0}], prev_net}}); prev_net = input_net; } } @@ -311,7 +325,8 @@ std::unique_ptr RamGen::makeDecoder( prefix, fmt::format("buf_port{}", port), buffer_cell_, - {{"A", decoder_out_net}, {"X", selects[port]}}); + {{buffer_ports_[{PortRoleType::DataIn, 0}], decoder_out_net}, + {buffer_ports_[{PortRoleType::DataOut, 0}], selects[port]}}); } return word_cell; @@ -353,7 +368,8 @@ dbMaster* RamGen::findMaster( continue; } - auto port_iter = liberty->portIterator(); + auto port_iter = std::unique_ptr( + liberty->portIterator()); sta::ConcretePort* out = nullptr; while (port_iter->hasNext()) { @@ -369,7 +385,6 @@ dbMaster* RamGen::findMaster( } } - delete port_iter; if (!out || !match(out->libertyPort())) { continue; } @@ -388,6 +403,91 @@ dbMaster* RamGen::findMaster( return best; } +std::map RamGen::buildPortMap(dbMaster* master) +{ + auto sta_cell = network_->dbToSta(master); + auto liberty = network_->libertyCell(sta_cell); + std::map pin_map; + int in_idx = 0; + + // needed since there is no tristate enable flag + std::string tri_enable_name; + + auto port_iter + = std::unique_ptr(liberty->portIterator()); + while (port_iter->hasNext()) { + auto concrete = port_iter->next(); + auto lib_port = concrete->libertyPort(); + auto dir = concrete->direction(); + + if (lib_port->isPwrGnd()) { + auto pwr_gnd_type = lib_port->pwrGndType(); + if (pwr_gnd_type == sta::PwrGndType::primary_power) { + pin_map[{PortRoleType::Power, 0}] = lib_port->name(); + } else if (pwr_gnd_type == sta::PwrGndType::primary_ground) { + pin_map[{PortRoleType::Ground, 0}] = lib_port->name(); + } + } else if (lib_port->isClock() || lib_port->isRegClk() + || lib_port->isClockGateClock()) { + pin_map[{PortRoleType::Clock, 0}] = lib_port->name(); + } else if (dir->isTristate()) { + pin_map[{PortRoleType::DataOut, 0}] = lib_port->name(); + auto tri_expr = lib_port->tristateEnable(); + // can only get the name of enable once the output is found to be a + // tristate + if (tri_expr && tri_expr->op() == sta::FuncExpr::Op::port) { + tri_enable_name = tri_expr->port()->name(); + } else if (tri_expr && tri_expr->op() == sta::FuncExpr::Op::not_) { + tri_enable_name = tri_expr->left()->port()->name(); + } + } else if (dir->isAnyOutput()) { // catches isOutput() + pin_map[{PortRoleType::DataOut, 0}] = lib_port->name(); + } else if (dir->isInput()) { + pin_map[{PortRoleType::DataIn, in_idx++}] = lib_port->name(); + } + } + + // second pass for to assign tristate enable correct role + // first pass can not classify without a dedicated tristate flag + if (!tri_enable_name.empty()) { + // find and remove it from DataIn + for (auto it = pin_map.begin(); it != pin_map.end(); ++it) { + if (it->second == tri_enable_name + && it->first.type == PortRoleType::DataIn) { + pin_map.erase(it); + break; + } + } + pin_map[{PortRoleType::TriEnable, 0}] = tri_enable_name; + } + + // validate power/ground after classification is complete + int power_count = 0, ground_count = 0; + for (auto& [role, name] : pin_map) { + if (role.type == PortRoleType::Power) { + ++power_count; + } + if (role.type == PortRoleType::Ground) { + ++ground_count; + } + } + if (power_count != 1) { + logger_->error(RAM, + 28, + "Cell {} must have exactly 1 primary power pin, found {}", + master->getName(), + power_count); + } + if (ground_count != 1) { + logger_->error(RAM, + 29, + "Cell {} must have exactly 1 primary ground pin, found {}", + master->getName(), + ground_count); + } + return pin_map; +} + void RamGen::findMasters() { if (!inv_cell_) { @@ -397,6 +497,7 @@ void RamGen::findMasters() }, "inverter"); } + inv_ports_ = buildPortMap(inv_cell_); if (!tristate_cell_) { tristate_cell_ = findMaster( @@ -409,6 +510,7 @@ void RamGen::findMasters() }, "tristate"); } + tristate_ports_ = buildPortMap(tristate_cell_); if (!and2_cell_) { and2_cell_ = findMaster( @@ -423,21 +525,33 @@ void RamGen::findMasters() }, "and2"); } + and2_ports_ = buildPortMap(and2_cell_); if (!storage_cell_) { // FIXME + // Still needs changes to get right type of flip-flop storage_cell_ = findMaster( [](sta::LibertyPort* port) { - if (!port->direction()->isOutput()) { + if (!port->isRegOutput()) { return false; } - auto function = port->function(); - return function && function->op() == sta::FuncExpr::Op::and_ - && function->left()->op() == sta::FuncExpr::Op::port - && function->right()->op() == sta::FuncExpr::Op::port; + // looking for DFF specifically + auto cell = port->libertyCell(); + auto port_iter = cell->portIterator(); + while (port_iter->hasNext()) { + auto p = port_iter->next()->libertyPort(); + // check to filter out latches + if (p && p->isLatchData()) { + delete port_iter; + return false; + } + } + delete port_iter; + return true; }, "storage"); } + storage_ports_ = buildPortMap(storage_cell_); if (!clock_gate_cell_) { clock_gate_cell_ = findMaster( @@ -446,12 +560,15 @@ void RamGen::findMasters() }, "clock gate"); } + clock_gate_ports_ = buildPortMap(clock_gate_cell_); + // for input buffers if (!buffer_cell_) { buffer_cell_ = findMaster( [](sta::LibertyPort* port) { return port->libertyCell()->isBuffer(); }, "buffer"); } + buffer_ports_ = buildPortMap(buffer_cell_); } void RamGen::ramPdngen(const char* power_pin, @@ -496,7 +613,6 @@ void RamGen::ramPdngen(const char* power_pin, ground_net->setSpecial(); ground_net->setSigType(odb::dbSigType::GROUND); - // find a way to get the power and ground net names associated with cells used block_->addGlobalConnect(nullptr, ".*", power_pin, power_net, true); block_->addGlobalConnect(nullptr, ".*", ground_pin, ground_net, true); @@ -775,12 +891,13 @@ void RamGen::generate(const int mask_size, for (int bit = 0; bit < mask_size; ++bit) { int bit_idx = bit + slice * mask_size; auto buffer_grid_cell = std::make_unique(); - makeInst( - buffer_grid_cell.get(), - "buffer", - fmt::format("in[{}]", bit_idx), - buffer_cell_, - {{"A", data_inputs_[bit_idx]->getNet()}, {"X", D_nets[bit_idx]}}); + makeInst(buffer_grid_cell.get(), + "buffer", + fmt::format("in[{}]", bit_idx), + buffer_cell_, + {{buffer_ports_[{PortRoleType::DataIn, 0}], + data_inputs_[bit_idx]->getNet()}, + {buffer_ports_[{PortRoleType::DataOut, 0}], D_nets[bit_idx]}}); ram_grid_.addCell(std::move(buffer_grid_cell), bit_idx + slice); } } @@ -790,11 +907,13 @@ void RamGen::generate(const int mask_size, if (num_inputs > 1) { for (int i = num_inputs - 1; i >= 0; --i) { auto inv_grid_cell = std::make_unique(); - makeInst(inv_grid_cell.get(), - "decoder", - fmt::format("inv_{}", i), - inv_cell_, - {{"A", addr_inputs_[i]->getNet()}, {"Y", inv_addr[i]}}); + makeInst( + inv_grid_cell.get(), + "decoder", + fmt::format("inv_{}", i), + inv_cell_, + {{inv_ports_[{PortRoleType::DataIn, 0}], addr_inputs_[i]->getNet()}, + {inv_ports_[{PortRoleType::DataOut, 0}], inv_addr[i]}}); cell_inv_layout->addCell(std::move(inv_grid_cell)); for (int filler_count = 0; filler_count < num_inputs - 1; ++filler_count) { @@ -803,11 +922,13 @@ void RamGen::generate(const int mask_size, } } else { auto inv_grid_cell = std::make_unique(); - makeInst(inv_grid_cell.get(), - "decoder", - fmt::format("inv_{}", 0), - inv_cell_, - {{"A", addr_inputs_[0]->getNet()}, {"Y", inv_addr[0]}}); + makeInst( + inv_grid_cell.get(), + "decoder", + fmt::format("inv_{}", 0), + inv_cell_, + {{inv_ports_[{PortRoleType::DataIn, 0}], addr_inputs_[0]->getNet()}, + {inv_ports_[{PortRoleType::DataOut, 0}], inv_addr[0]}}); cell_inv_layout->addCell(std::move(inv_grid_cell)); } diff --git a/src/ram/test/CMakeLists.txt b/src/ram/test/CMakeLists.txt index c8f90ea696b..b2ec75827ba 100644 --- a/src/ram/test/CMakeLists.txt +++ b/src/ram/test/CMakeLists.txt @@ -1,6 +1,7 @@ or_integration_tests( "ram" TESTS - make_8x8 + make_8x8_sky130 + make_7x7_nangate45 ) diff --git a/src/ram/test/Nangate45 b/src/ram/test/Nangate45 new file mode 120000 index 00000000000..7f1df955c57 --- /dev/null +++ b/src/ram/test/Nangate45 @@ -0,0 +1 @@ +../../../test/Nangate45 \ No newline at end of file diff --git a/src/ram/test/make_7x7_nangate45.defok b/src/ram/test/make_7x7_nangate45.defok new file mode 100644 index 00000000000..f539370c5d5 --- /dev/null +++ b/src/ram/test/make_7x7_nangate45.defok @@ -0,0 +1,1812 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN RAM7x7 ; +UNITS DISTANCE MICRONS 100 ; +DIEAREA ( 0 0 ) ( 3952 1120 ) ; +ROW RAM_ROW0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 208 BY 1 STEP 19 0 ; +ROW RAM_ROW1 FreePDK45_38x28_10R_NP_162NW_34O 0 140 FS DO 208 BY 1 STEP 19 0 ; +ROW RAM_ROW2 FreePDK45_38x28_10R_NP_162NW_34O 0 280 N DO 208 BY 1 STEP 19 0 ; +ROW RAM_ROW3 FreePDK45_38x28_10R_NP_162NW_34O 0 420 FS DO 208 BY 1 STEP 19 0 ; +ROW RAM_ROW4 FreePDK45_38x28_10R_NP_162NW_34O 0 560 N DO 208 BY 1 STEP 19 0 ; +ROW RAM_ROW5 FreePDK45_38x28_10R_NP_162NW_34O 0 700 FS DO 208 BY 1 STEP 19 0 ; +ROW RAM_ROW6 FreePDK45_38x28_10R_NP_162NW_34O 0 840 N DO 208 BY 1 STEP 19 0 ; +ROW RAM_ROW7 FreePDK45_38x28_10R_NP_162NW_34O 0 980 FS DO 208 BY 1 STEP 19 0 ; +TRACKS X 9 DO 282 STEP 14 LAYER metal1 ; +TRACKS Y 7 DO 80 STEP 14 LAYER metal1 ; +TRACKS X 9 DO 208 STEP 19 LAYER metal2 ; +TRACKS Y 7 DO 59 STEP 19 LAYER metal2 ; +TRACKS X 9 DO 282 STEP 14 LAYER metal3 ; +TRACKS Y 7 DO 80 STEP 14 LAYER metal3 ; +TRACKS X 9 DO 141 STEP 28 LAYER metal4 ; +TRACKS Y 7 DO 40 STEP 28 LAYER metal4 ; +TRACKS X 9 DO 141 STEP 28 LAYER metal5 ; +TRACKS Y 7 DO 40 STEP 28 LAYER metal5 ; +TRACKS X 9 DO 141 STEP 28 LAYER metal6 ; +TRACKS Y 7 DO 40 STEP 28 LAYER metal6 ; +TRACKS X 89 DO 49 STEP 80 LAYER metal7 ; +TRACKS Y 87 DO 13 STEP 80 LAYER metal7 ; +TRACKS X 89 DO 49 STEP 80 LAYER metal8 ; +TRACKS Y 87 DO 13 STEP 80 LAYER metal8 ; +TRACKS X 169 DO 24 STEP 160 LAYER metal9 ; +TRACKS Y 167 DO 6 STEP 160 LAYER metal9 ; +TRACKS X 169 DO 24 STEP 160 LAYER metal10 ; +TRACKS Y 167 DO 6 STEP 160 LAYER metal10 ; +GCELLGRID X 0 DO 13 STEP 285 ; +GCELLGRID Y 0 DO 3 STEP 285 ; +VIAS 3 ; + - via1_2_280_160_1_1_300_300 + VIARULE Via1Array-0 + CUTSIZE 7 7 + LAYERS metal1 via1 metal2 + CUTSPACING 8 8 + ENCLOSURE 3 0 3 3 ; + - via2_3_280_160_1_1_320_320 + VIARULE Via2Array-0 + CUTSIZE 7 7 + LAYERS metal2 via2 metal3 + CUTSPACING 9 9 + ENCLOSURE 3 3 3 3 ; + - via3_4_280_160_1_1_320_320 + VIARULE Via3Array-0 + CUTSIZE 7 7 + LAYERS metal3 via3 metal4 + CUTSPACING 9 9 + ENCLOSURE 3 3 3 3 ; +END VIAS +COMPONENTS 218 ; + - FILLER_1_206 FILLCELL_X2 + SOURCE DIST + PLACED ( 3914 140 ) FS ; + - FILLER_2_206 FILLCELL_X2 + SOURCE DIST + PLACED ( 3914 280 ) N ; + - FILLER_4_206 FILLCELL_X2 + SOURCE DIST + PLACED ( 3914 560 ) N ; + - FILLER_5_206 FILLCELL_X2 + SOURCE DIST + PLACED ( 3914 700 ) FS ; + - FILLER_7_100 FILLCELL_X2 + SOURCE DIST + PLACED ( 1900 980 ) FS ; + - FILLER_7_106 FILLCELL_X8 + SOURCE DIST + PLACED ( 2014 980 ) FS ; + - FILLER_7_114 FILLCELL_X8 + SOURCE DIST + PLACED ( 2166 980 ) FS ; + - FILLER_7_12 FILLCELL_X8 + SOURCE DIST + PLACED ( 228 980 ) FS ; + - FILLER_7_122 FILLCELL_X4 + SOURCE DIST + PLACED ( 2318 980 ) FS ; + - FILLER_7_126 FILLCELL_X2 + SOURCE DIST + PLACED ( 2394 980 ) FS ; + - FILLER_7_131 FILLCELL_X8 + SOURCE DIST + PLACED ( 2489 980 ) FS ; + - FILLER_7_139 FILLCELL_X8 + SOURCE DIST + PLACED ( 2641 980 ) FS ; + - FILLER_7_147 FILLCELL_X4 + SOURCE DIST + PLACED ( 2793 980 ) FS ; + - FILLER_7_151 FILLCELL_X2 + SOURCE DIST + PLACED ( 2869 980 ) FS ; + - FILLER_7_157 FILLCELL_X8 + SOURCE DIST + PLACED ( 2983 980 ) FS ; + - FILLER_7_165 FILLCELL_X8 + SOURCE DIST + PLACED ( 3135 980 ) FS ; + - FILLER_7_173 FILLCELL_X8 + SOURCE DIST + PLACED ( 3287 980 ) FS ; + - FILLER_7_181 FILLCELL_X8 + SOURCE DIST + PLACED ( 3439 980 ) FS ; + - FILLER_7_189 FILLCELL_X8 + SOURCE DIST + PLACED ( 3591 980 ) FS ; + - FILLER_7_197 FILLCELL_X8 + SOURCE DIST + PLACED ( 3743 980 ) FS ; + - FILLER_7_20 FILLCELL_X4 + SOURCE DIST + PLACED ( 380 980 ) FS ; + - FILLER_7_206 FILLCELL_X2 + SOURCE DIST + PLACED ( 3914 980 ) FS ; + - FILLER_7_24 FILLCELL_X2 + SOURCE DIST + PLACED ( 456 980 ) FS ; + - FILLER_7_29 FILLCELL_X8 + SOURCE DIST + PLACED ( 551 980 ) FS ; + - FILLER_7_37 FILLCELL_X8 + SOURCE DIST + PLACED ( 703 980 ) FS ; + - FILLER_7_4 FILLCELL_X8 + SOURCE DIST + PLACED ( 76 980 ) FS ; + - FILLER_7_45 FILLCELL_X4 + SOURCE DIST + PLACED ( 855 980 ) FS ; + - FILLER_7_49 FILLCELL_X2 + SOURCE DIST + PLACED ( 931 980 ) FS ; + - FILLER_7_55 FILLCELL_X8 + SOURCE DIST + PLACED ( 1045 980 ) FS ; + - FILLER_7_63 FILLCELL_X8 + SOURCE DIST + PLACED ( 1197 980 ) FS ; + - FILLER_7_71 FILLCELL_X4 + SOURCE DIST + PLACED ( 1349 980 ) FS ; + - FILLER_7_75 FILLCELL_X2 + SOURCE DIST + PLACED ( 1425 980 ) FS ; + - FILLER_7_80 FILLCELL_X8 + SOURCE DIST + PLACED ( 1520 980 ) FS ; + - FILLER_7_88 FILLCELL_X8 + SOURCE DIST + PLACED ( 1672 980 ) FS ; + - FILLER_7_96 FILLCELL_X4 + SOURCE DIST + PLACED ( 1824 980 ) FS ; + - buffer.in[0] BUF_X1 + PLACED ( 19 980 ) FS ; + - buffer.in[1] BUF_X1 + PLACED ( 494 980 ) FS ; + - buffer.in[2] BUF_X1 + PLACED ( 988 980 ) FS ; + - buffer.in[3] BUF_X1 + PLACED ( 1463 980 ) FS ; + - buffer.in[4] BUF_X1 + PLACED ( 1957 980 ) FS ; + - buffer.in[5] BUF_X1 + PLACED ( 2432 980 ) FS ; + - buffer.in[6] BUF_X1 + PLACED ( 2926 980 ) FS ; + - decoder.inv_0 INV_X1 + PLACED ( 3914 840 ) N ; + - decoder.inv_1 INV_X1 + PLACED ( 3914 420 ) FS ; + - decoder.inv_2 INV_X1 + PLACED ( 3914 0 ) N ; + - decoder_0.and_layer0 AND2_X1 + PLACED ( 3762 0 ) N ; + - decoder_0.buf_port0 BUF_X1 + PLACED ( 3838 0 ) N ; + - decoder_1.and_layer0 AND2_X1 + PLACED ( 3762 140 ) FS ; + - decoder_1.buf_port0 BUF_X1 + PLACED ( 3838 140 ) FS ; + - decoder_2.and_layer0 AND2_X1 + PLACED ( 3762 280 ) N ; + - decoder_2.buf_port0 BUF_X1 + PLACED ( 3838 280 ) N ; + - decoder_3.and_layer0 AND2_X1 + PLACED ( 3762 420 ) FS ; + - decoder_3.buf_port0 BUF_X1 + PLACED ( 3838 420 ) FS ; + - decoder_4.and_layer0 AND2_X1 + PLACED ( 3762 560 ) N ; + - decoder_4.buf_port0 BUF_X1 + PLACED ( 3838 560 ) N ; + - decoder_5.and_layer0 AND2_X1 + PLACED ( 3762 700 ) FS ; + - decoder_5.buf_port0 BUF_X1 + PLACED ( 3838 700 ) FS ; + - decoder_6.and_layer0 AND2_X1 + PLACED ( 3762 840 ) N ; + - decoder_6.buf_port0 BUF_X1 + PLACED ( 3838 840 ) N ; + - storage_0_0.bit0.bit DFF_X1 + PLACED ( 19 0 ) N ; + - storage_0_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 0 ) N ; + - storage_0_0.bit1.bit DFF_X1 + PLACED ( 494 0 ) N ; + - storage_0_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 0 ) N ; + - storage_0_0.bit2.bit DFF_X1 + PLACED ( 988 0 ) N ; + - storage_0_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 0 ) N ; + - storage_0_0.bit3.bit DFF_X1 + PLACED ( 1463 0 ) N ; + - storage_0_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 0 ) N ; + - storage_0_0.bit4.bit DFF_X1 + PLACED ( 1957 0 ) N ; + - storage_0_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 0 ) N ; + - storage_0_0.bit5.bit DFF_X1 + PLACED ( 2432 0 ) N ; + - storage_0_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 0 ) N ; + - storage_0_0.bit6.bit DFF_X1 + PLACED ( 2926 0 ) N ; + - storage_0_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 0 ) N ; + - storage_0_0.cg CLKGATE_X1 + PLACED ( 3401 0 ) N ; + - storage_0_0.gcand AND2_X1 + PLACED ( 3648 0 ) N ; + - storage_0_0.select_inv_0 INV_X1 + PLACED ( 3724 0 ) N ; + - storage_1_0.bit0.bit DFF_X1 + PLACED ( 19 140 ) FS ; + - storage_1_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 140 ) FS ; + - storage_1_0.bit1.bit DFF_X1 + PLACED ( 494 140 ) FS ; + - storage_1_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 140 ) FS ; + - storage_1_0.bit2.bit DFF_X1 + PLACED ( 988 140 ) FS ; + - storage_1_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 140 ) FS ; + - storage_1_0.bit3.bit DFF_X1 + PLACED ( 1463 140 ) FS ; + - storage_1_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 140 ) FS ; + - storage_1_0.bit4.bit DFF_X1 + PLACED ( 1957 140 ) FS ; + - storage_1_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 140 ) FS ; + - storage_1_0.bit5.bit DFF_X1 + PLACED ( 2432 140 ) FS ; + - storage_1_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 140 ) FS ; + - storage_1_0.bit6.bit DFF_X1 + PLACED ( 2926 140 ) FS ; + - storage_1_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 140 ) FS ; + - storage_1_0.cg CLKGATE_X1 + PLACED ( 3401 140 ) FS ; + - storage_1_0.gcand AND2_X1 + PLACED ( 3648 140 ) FS ; + - storage_1_0.select_inv_0 INV_X1 + PLACED ( 3724 140 ) FS ; + - storage_2_0.bit0.bit DFF_X1 + PLACED ( 19 280 ) N ; + - storage_2_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 280 ) N ; + - storage_2_0.bit1.bit DFF_X1 + PLACED ( 494 280 ) N ; + - storage_2_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 280 ) N ; + - storage_2_0.bit2.bit DFF_X1 + PLACED ( 988 280 ) N ; + - storage_2_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 280 ) N ; + - storage_2_0.bit3.bit DFF_X1 + PLACED ( 1463 280 ) N ; + - storage_2_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 280 ) N ; + - storage_2_0.bit4.bit DFF_X1 + PLACED ( 1957 280 ) N ; + - storage_2_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 280 ) N ; + - storage_2_0.bit5.bit DFF_X1 + PLACED ( 2432 280 ) N ; + - storage_2_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 280 ) N ; + - storage_2_0.bit6.bit DFF_X1 + PLACED ( 2926 280 ) N ; + - storage_2_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 280 ) N ; + - storage_2_0.cg CLKGATE_X1 + PLACED ( 3401 280 ) N ; + - storage_2_0.gcand AND2_X1 + PLACED ( 3648 280 ) N ; + - storage_2_0.select_inv_0 INV_X1 + PLACED ( 3724 280 ) N ; + - storage_3_0.bit0.bit DFF_X1 + PLACED ( 19 420 ) FS ; + - storage_3_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 420 ) FS ; + - storage_3_0.bit1.bit DFF_X1 + PLACED ( 494 420 ) FS ; + - storage_3_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 420 ) FS ; + - storage_3_0.bit2.bit DFF_X1 + PLACED ( 988 420 ) FS ; + - storage_3_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 420 ) FS ; + - storage_3_0.bit3.bit DFF_X1 + PLACED ( 1463 420 ) FS ; + - storage_3_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 420 ) FS ; + - storage_3_0.bit4.bit DFF_X1 + PLACED ( 1957 420 ) FS ; + - storage_3_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 420 ) FS ; + - storage_3_0.bit5.bit DFF_X1 + PLACED ( 2432 420 ) FS ; + - storage_3_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 420 ) FS ; + - storage_3_0.bit6.bit DFF_X1 + PLACED ( 2926 420 ) FS ; + - storage_3_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 420 ) FS ; + - storage_3_0.cg CLKGATE_X1 + PLACED ( 3401 420 ) FS ; + - storage_3_0.gcand AND2_X1 + PLACED ( 3648 420 ) FS ; + - storage_3_0.select_inv_0 INV_X1 + PLACED ( 3724 420 ) FS ; + - storage_4_0.bit0.bit DFF_X1 + PLACED ( 19 560 ) N ; + - storage_4_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 560 ) N ; + - storage_4_0.bit1.bit DFF_X1 + PLACED ( 494 560 ) N ; + - storage_4_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 560 ) N ; + - storage_4_0.bit2.bit DFF_X1 + PLACED ( 988 560 ) N ; + - storage_4_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 560 ) N ; + - storage_4_0.bit3.bit DFF_X1 + PLACED ( 1463 560 ) N ; + - storage_4_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 560 ) N ; + - storage_4_0.bit4.bit DFF_X1 + PLACED ( 1957 560 ) N ; + - storage_4_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 560 ) N ; + - storage_4_0.bit5.bit DFF_X1 + PLACED ( 2432 560 ) N ; + - storage_4_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 560 ) N ; + - storage_4_0.bit6.bit DFF_X1 + PLACED ( 2926 560 ) N ; + - storage_4_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 560 ) N ; + - storage_4_0.cg CLKGATE_X1 + PLACED ( 3401 560 ) N ; + - storage_4_0.gcand AND2_X1 + PLACED ( 3648 560 ) N ; + - storage_4_0.select_inv_0 INV_X1 + PLACED ( 3724 560 ) N ; + - storage_5_0.bit0.bit DFF_X1 + PLACED ( 19 700 ) FS ; + - storage_5_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 700 ) FS ; + - storage_5_0.bit1.bit DFF_X1 + PLACED ( 494 700 ) FS ; + - storage_5_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 700 ) FS ; + - storage_5_0.bit2.bit DFF_X1 + PLACED ( 988 700 ) FS ; + - storage_5_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 700 ) FS ; + - storage_5_0.bit3.bit DFF_X1 + PLACED ( 1463 700 ) FS ; + - storage_5_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 700 ) FS ; + - storage_5_0.bit4.bit DFF_X1 + PLACED ( 1957 700 ) FS ; + - storage_5_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 700 ) FS ; + - storage_5_0.bit5.bit DFF_X1 + PLACED ( 2432 700 ) FS ; + - storage_5_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 700 ) FS ; + - storage_5_0.bit6.bit DFF_X1 + PLACED ( 2926 700 ) FS ; + - storage_5_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 700 ) FS ; + - storage_5_0.cg CLKGATE_X1 + PLACED ( 3401 700 ) FS ; + - storage_5_0.gcand AND2_X1 + PLACED ( 3648 700 ) FS ; + - storage_5_0.select_inv_0 INV_X1 + PLACED ( 3724 700 ) FS ; + - storage_6_0.bit0.bit DFF_X1 + PLACED ( 19 840 ) N ; + - storage_6_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 840 ) N ; + - storage_6_0.bit1.bit DFF_X1 + PLACED ( 494 840 ) N ; + - storage_6_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 840 ) N ; + - storage_6_0.bit2.bit DFF_X1 + PLACED ( 988 840 ) N ; + - storage_6_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 840 ) N ; + - storage_6_0.bit3.bit DFF_X1 + PLACED ( 1463 840 ) N ; + - storage_6_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 840 ) N ; + - storage_6_0.bit4.bit DFF_X1 + PLACED ( 1957 840 ) N ; + - storage_6_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 840 ) N ; + - storage_6_0.bit5.bit DFF_X1 + PLACED ( 2432 840 ) N ; + - storage_6_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 840 ) N ; + - storage_6_0.bit6.bit DFF_X1 + PLACED ( 2926 840 ) N ; + - storage_6_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 840 ) N ; + - storage_6_0.cg CLKGATE_X1 + PLACED ( 3401 840 ) N ; + - storage_6_0.gcand AND2_X1 + PLACED ( 3648 840 ) N ; + - storage_6_0.select_inv_0 INV_X1 + PLACED ( 3724 840 ) N ; + - tapcell.cell0_0 TAPCELL_X1 + PLACED ( 0 0 ) N ; + - tapcell.cell0_1 TAPCELL_X1 + PLACED ( 0 140 ) FS ; + - tapcell.cell0_2 TAPCELL_X1 + PLACED ( 0 280 ) N ; + - tapcell.cell0_3 TAPCELL_X1 + PLACED ( 0 420 ) FS ; + - tapcell.cell0_4 TAPCELL_X1 + PLACED ( 0 560 ) N ; + - tapcell.cell0_5 TAPCELL_X1 + PLACED ( 0 700 ) FS ; + - tapcell.cell0_6 TAPCELL_X1 + PLACED ( 0 840 ) N ; + - tapcell.cell0_7 TAPCELL_X1 + PLACED ( 0 980 ) FS ; + - tapcell.cell1_0 TAPCELL_X1 + PLACED ( 969 0 ) N ; + - tapcell.cell1_1 TAPCELL_X1 + PLACED ( 969 140 ) FS ; + - tapcell.cell1_2 TAPCELL_X1 + PLACED ( 969 280 ) N ; + - tapcell.cell1_3 TAPCELL_X1 + PLACED ( 969 420 ) FS ; + - tapcell.cell1_4 TAPCELL_X1 + PLACED ( 969 560 ) N ; + - tapcell.cell1_5 TAPCELL_X1 + PLACED ( 969 700 ) FS ; + - tapcell.cell1_6 TAPCELL_X1 + PLACED ( 969 840 ) N ; + - tapcell.cell1_7 TAPCELL_X1 + PLACED ( 969 980 ) FS ; + - tapcell.cell2_0 TAPCELL_X1 + PLACED ( 1938 0 ) N ; + - tapcell.cell2_1 TAPCELL_X1 + PLACED ( 1938 140 ) FS ; + - tapcell.cell2_2 TAPCELL_X1 + PLACED ( 1938 280 ) N ; + - tapcell.cell2_3 TAPCELL_X1 + PLACED ( 1938 420 ) FS ; + - tapcell.cell2_4 TAPCELL_X1 + PLACED ( 1938 560 ) N ; + - tapcell.cell2_5 TAPCELL_X1 + PLACED ( 1938 700 ) FS ; + - tapcell.cell2_6 TAPCELL_X1 + PLACED ( 1938 840 ) N ; + - tapcell.cell2_7 TAPCELL_X1 + PLACED ( 1938 980 ) FS ; + - tapcell.cell3_0 TAPCELL_X1 + PLACED ( 2907 0 ) N ; + - tapcell.cell3_1 TAPCELL_X1 + PLACED ( 2907 140 ) FS ; + - tapcell.cell3_2 TAPCELL_X1 + PLACED ( 2907 280 ) N ; + - tapcell.cell3_3 TAPCELL_X1 + PLACED ( 2907 420 ) FS ; + - tapcell.cell3_4 TAPCELL_X1 + PLACED ( 2907 560 ) N ; + - tapcell.cell3_5 TAPCELL_X1 + PLACED ( 2907 700 ) FS ; + - tapcell.cell3_6 TAPCELL_X1 + PLACED ( 2907 840 ) N ; + - tapcell.cell3_7 TAPCELL_X1 + PLACED ( 2907 980 ) FS ; + - tapcell.cell4_0 TAPCELL_X1 + PLACED ( 3895 0 ) N ; + - tapcell.cell4_1 TAPCELL_X1 + PLACED ( 3895 140 ) FS ; + - tapcell.cell4_2 TAPCELL_X1 + PLACED ( 3895 280 ) N ; + - tapcell.cell4_3 TAPCELL_X1 + PLACED ( 3895 420 ) FS ; + - tapcell.cell4_4 TAPCELL_X1 + PLACED ( 3895 560 ) N ; + - tapcell.cell4_5 TAPCELL_X1 + PLACED ( 3895 700 ) FS ; + - tapcell.cell4_6 TAPCELL_X1 + PLACED ( 3895 840 ) N ; + - tapcell.cell4_7 TAPCELL_X1 + PLACED ( 3895 980 ) FS ; +END COMPONENTS +PINS 21 ; + - D[0] + NET D[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 121 1113 ) N ; + - D[1] + NET D[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 513 1113 ) N ; + - D[2] + NET D[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 1017 1113 ) N ; + - D[3] + NET D[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 1465 1113 ) N ; + - D[4] + NET D[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 1969 1113 ) N ; + - D[5] + NET D[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 2417 1113 ) N ; + - D[6] + NET D[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 2921 1113 ) N ; + - Q[0] + NET Q[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 345 1113 ) N ; + - Q[1] + NET Q[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 849 1113 ) N ; + - Q[2] + NET Q[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 1297 1113 ) N ; + - Q[3] + NET Q[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 1745 1113 ) N ; + - Q[4] + NET Q[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 2305 1113 ) N ; + - Q[5] + NET Q[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 2753 1113 ) N ; + - Q[6] + NET Q[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + PLACED ( 3257 1113 ) N ; + - VDD + NET VDD + SPECIAL + DIRECTION INOUT + USE POWER + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + LAYER metal4 ( -7 -1113 ) ( 7 -1099 ) + + LAYER metal4 ( -907 -7 ) ( -893 7 ) + + LAYER metal4 ( -907 -1113 ) ( -893 -1099 ) + + LAYER metal4 ( -1807 -7 ) ( -1793 7 ) + + LAYER metal4 ( -1807 -1113 ) ( -1793 -1099 ) + + LAYER metal4 ( -2707 -7 ) ( -2693 7 ) + + LAYER metal4 ( -2707 -1113 ) ( -2693 -1099 ) + + LAYER metal1 ( 795 -137 ) ( 802 -129 ) + + LAYER metal1 ( -3150 -137 ) ( -3143 -129 ) + + LAYER metal1 ( 795 -417 ) ( 802 -409 ) + + LAYER metal1 ( -3150 -417 ) ( -3143 -409 ) + + LAYER metal1 ( 795 -697 ) ( 802 -689 ) + + LAYER metal1 ( -3150 -697 ) ( -3143 -689 ) + + LAYER metal1 ( 795 -977 ) ( 802 -969 ) + + LAYER metal1 ( -3150 -977 ) ( -3143 -969 ) + + FIXED ( 3150 1113 ) N ; + - VSS + NET VSS + SPECIAL + DIRECTION INOUT + USE GROUND + + PORT + + LAYER metal4 ( -7 -7 ) ( 7 7 ) + + LAYER metal4 ( -7 -1113 ) ( 7 -1099 ) + + LAYER metal4 ( -907 -7 ) ( -893 7 ) + + LAYER metal4 ( -907 -1113 ) ( -893 -1099 ) + + LAYER metal4 ( -1807 -7 ) ( -1793 7 ) + + LAYER metal4 ( -1807 -1113 ) ( -1793 -1099 ) + + LAYER metal4 ( -2707 -7 ) ( -2693 7 ) + + LAYER metal4 ( -2707 -1113 ) ( -2693 -1099 ) + + LAYER metal1 ( 345 3 ) ( 352 11 ) + + LAYER metal1 ( -3600 3 ) ( -3593 11 ) + + LAYER metal1 ( 345 -277 ) ( 352 -269 ) + + LAYER metal1 ( -3600 -277 ) ( -3593 -269 ) + + LAYER metal1 ( 345 -557 ) ( 352 -549 ) + + LAYER metal1 ( -3600 -557 ) ( -3593 -549 ) + + LAYER metal1 ( 345 -837 ) ( 352 -829 ) + + LAYER metal1 ( -3600 -837 ) ( -3593 -829 ) + + LAYER metal1 ( 345 -1117 ) ( 352 -1109 ) + + LAYER metal1 ( -3600 -1117 ) ( -3593 -1109 ) + + FIXED ( 3600 1113 ) N ; + - addr[0] + NET addr[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -3 -3 ) ( 4 4 ) + + PLACED ( 3948 230 ) N ; + - addr[1] + NET addr[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -3 -3 ) ( 4 4 ) + + PLACED ( 3948 342 ) N ; + - addr[2] + NET addr[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -3 -3 ) ( 4 4 ) + + PLACED ( 3948 118 ) N ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -3 -3 ) ( 4 4 ) + + PLACED ( 3948 146 ) N ; + - we[0] + NET we[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal3 ( -3 -3 ) ( 4 4 ) + + PLACED ( 3948 174 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD ( PIN VDD ) ( tapcell.cell4_7 VDD ) ( tapcell.cell4_6 VDD ) ( tapcell.cell4_5 VDD ) ( tapcell.cell4_4 VDD ) ( tapcell.cell4_3 VDD ) ( tapcell.cell4_2 VDD ) + ( tapcell.cell4_1 VDD ) ( tapcell.cell4_0 VDD ) ( tapcell.cell3_7 VDD ) ( tapcell.cell3_6 VDD ) ( tapcell.cell3_5 VDD ) ( tapcell.cell3_4 VDD ) ( tapcell.cell3_3 VDD ) ( tapcell.cell3_2 VDD ) + ( tapcell.cell3_1 VDD ) ( tapcell.cell3_0 VDD ) ( tapcell.cell2_7 VDD ) ( tapcell.cell2_6 VDD ) ( tapcell.cell2_5 VDD ) ( tapcell.cell2_4 VDD ) ( tapcell.cell2_3 VDD ) ( tapcell.cell2_2 VDD ) + ( tapcell.cell2_1 VDD ) ( tapcell.cell2_0 VDD ) ( tapcell.cell1_7 VDD ) ( tapcell.cell1_6 VDD ) ( tapcell.cell1_5 VDD ) ( tapcell.cell1_4 VDD ) ( tapcell.cell1_3 VDD ) ( tapcell.cell1_2 VDD ) + ( tapcell.cell1_1 VDD ) ( tapcell.cell1_0 VDD ) ( tapcell.cell0_7 VDD ) ( tapcell.cell0_6 VDD ) ( tapcell.cell0_5 VDD ) ( tapcell.cell0_4 VDD ) ( tapcell.cell0_3 VDD ) ( tapcell.cell0_2 VDD ) + ( tapcell.cell0_1 VDD ) ( tapcell.cell0_0 VDD ) ( decoder.inv_0 VDD ) ( decoder.inv_1 VDD ) ( decoder.inv_2 VDD ) ( buffer.in[6] VDD ) ( buffer.in[5] VDD ) ( buffer.in[4] VDD ) + ( buffer.in[3] VDD ) ( buffer.in[2] VDD ) ( buffer.in[1] VDD ) ( buffer.in[0] VDD ) ( storage_6_0.select_inv_0 VDD ) ( storage_6_0.gcand VDD ) ( storage_6_0.cg VDD ) ( storage_6_0.bit6.obuf0 VDD ) + ( storage_6_0.bit6.bit VDD ) ( storage_6_0.bit5.obuf0 VDD ) ( storage_6_0.bit5.bit VDD ) ( storage_6_0.bit4.obuf0 VDD ) ( storage_6_0.bit4.bit VDD ) ( storage_6_0.bit3.obuf0 VDD ) ( storage_6_0.bit3.bit VDD ) ( storage_6_0.bit2.obuf0 VDD ) + ( storage_6_0.bit2.bit VDD ) ( storage_6_0.bit1.obuf0 VDD ) ( storage_6_0.bit1.bit VDD ) ( storage_6_0.bit0.obuf0 VDD ) ( storage_6_0.bit0.bit VDD ) ( storage_5_0.select_inv_0 VDD ) ( storage_5_0.gcand VDD ) ( storage_5_0.cg VDD ) + ( storage_5_0.bit6.obuf0 VDD ) ( storage_5_0.bit6.bit VDD ) ( storage_5_0.bit5.obuf0 VDD ) ( storage_5_0.bit5.bit VDD ) ( storage_5_0.bit4.obuf0 VDD ) ( storage_5_0.bit4.bit VDD ) ( storage_5_0.bit3.obuf0 VDD ) ( storage_5_0.bit3.bit VDD ) + ( storage_5_0.bit2.obuf0 VDD ) ( storage_5_0.bit2.bit VDD ) ( storage_5_0.bit1.obuf0 VDD ) ( storage_5_0.bit1.bit VDD ) ( storage_5_0.bit0.obuf0 VDD ) ( storage_5_0.bit0.bit VDD ) ( storage_4_0.select_inv_0 VDD ) ( storage_4_0.gcand VDD ) + ( storage_4_0.cg VDD ) ( storage_4_0.bit6.obuf0 VDD ) ( storage_4_0.bit6.bit VDD ) ( storage_4_0.bit5.obuf0 VDD ) ( storage_4_0.bit5.bit VDD ) ( storage_4_0.bit4.obuf0 VDD ) ( storage_4_0.bit4.bit VDD ) ( storage_4_0.bit3.obuf0 VDD ) + ( storage_4_0.bit3.bit VDD ) ( storage_4_0.bit2.obuf0 VDD ) ( storage_4_0.bit2.bit VDD ) ( storage_4_0.bit1.obuf0 VDD ) ( storage_4_0.bit1.bit VDD ) ( storage_4_0.bit0.obuf0 VDD ) ( storage_4_0.bit0.bit VDD ) ( storage_3_0.select_inv_0 VDD ) + ( storage_3_0.gcand VDD ) ( storage_3_0.cg VDD ) ( storage_3_0.bit6.obuf0 VDD ) ( storage_3_0.bit6.bit VDD ) ( storage_3_0.bit5.obuf0 VDD ) ( storage_3_0.bit5.bit VDD ) ( storage_3_0.bit4.obuf0 VDD ) ( storage_3_0.bit4.bit VDD ) + ( storage_3_0.bit3.obuf0 VDD ) ( storage_3_0.bit3.bit VDD ) ( storage_3_0.bit2.obuf0 VDD ) ( storage_3_0.bit2.bit VDD ) ( storage_3_0.bit1.obuf0 VDD ) ( storage_3_0.bit1.bit VDD ) ( storage_3_0.bit0.obuf0 VDD ) ( storage_3_0.bit0.bit VDD ) + ( storage_2_0.select_inv_0 VDD ) ( storage_2_0.gcand VDD ) ( storage_2_0.cg VDD ) ( storage_2_0.bit6.obuf0 VDD ) ( storage_2_0.bit6.bit VDD ) ( storage_2_0.bit5.obuf0 VDD ) ( storage_2_0.bit5.bit VDD ) ( storage_2_0.bit4.obuf0 VDD ) + ( storage_2_0.bit4.bit VDD ) ( storage_2_0.bit3.obuf0 VDD ) ( storage_2_0.bit3.bit VDD ) ( storage_2_0.bit2.obuf0 VDD ) ( storage_2_0.bit2.bit VDD ) ( storage_2_0.bit1.obuf0 VDD ) ( storage_2_0.bit1.bit VDD ) ( storage_2_0.bit0.obuf0 VDD ) + ( storage_2_0.bit0.bit VDD ) ( storage_1_0.select_inv_0 VDD ) ( storage_1_0.gcand VDD ) ( storage_1_0.cg VDD ) ( storage_1_0.bit6.obuf0 VDD ) ( storage_1_0.bit6.bit VDD ) ( storage_1_0.bit5.obuf0 VDD ) ( storage_1_0.bit5.bit VDD ) + ( storage_1_0.bit4.obuf0 VDD ) ( storage_1_0.bit4.bit VDD ) ( storage_1_0.bit3.obuf0 VDD ) ( storage_1_0.bit3.bit VDD ) ( storage_1_0.bit2.obuf0 VDD ) ( storage_1_0.bit2.bit VDD ) ( storage_1_0.bit1.obuf0 VDD ) ( storage_1_0.bit1.bit VDD ) + ( storage_1_0.bit0.obuf0 VDD ) ( storage_1_0.bit0.bit VDD ) ( storage_0_0.select_inv_0 VDD ) ( storage_0_0.gcand VDD ) ( storage_0_0.cg VDD ) ( storage_0_0.bit6.obuf0 VDD ) ( storage_0_0.bit6.bit VDD ) ( storage_0_0.bit5.obuf0 VDD ) + ( storage_0_0.bit5.bit VDD ) ( storage_0_0.bit4.obuf0 VDD ) ( storage_0_0.bit4.bit VDD ) ( storage_0_0.bit3.obuf0 VDD ) ( storage_0_0.bit3.bit VDD ) ( storage_0_0.bit2.obuf0 VDD ) ( storage_0_0.bit2.bit VDD ) ( storage_0_0.bit1.obuf0 VDD ) + ( storage_0_0.bit1.bit VDD ) ( storage_0_0.bit0.obuf0 VDD ) ( storage_0_0.bit0.bit VDD ) ( decoder_6.buf_port0 VDD ) ( decoder_6.and_layer0 VDD ) ( decoder_5.buf_port0 VDD ) ( decoder_5.and_layer0 VDD ) ( decoder_4.buf_port0 VDD ) + ( decoder_4.and_layer0 VDD ) ( decoder_3.buf_port0 VDD ) ( decoder_3.and_layer0 VDD ) ( decoder_2.buf_port0 VDD ) ( decoder_2.and_layer0 VDD ) ( decoder_1.buf_port0 VDD ) ( decoder_1.and_layer0 VDD ) ( decoder_0.buf_port0 VDD ) + ( decoder_0.and_layer0 VDD ) + USE POWER + + ROUTED metal4 14 + SHAPE STRIPE ( 3150 0 ) ( 3150 1120 ) + NEW metal4 14 + SHAPE STRIPE ( 2250 0 ) ( 2250 1120 ) + NEW metal4 14 + SHAPE STRIPE ( 1350 0 ) ( 1350 1120 ) + NEW metal4 14 + SHAPE STRIPE ( 450 0 ) ( 450 1120 ) + NEW metal1 8 + SHAPE FOLLOWPIN ( 0 980 ) ( 3952 980 ) + NEW metal1 8 + SHAPE FOLLOWPIN ( 0 700 ) ( 3952 700 ) + NEW metal1 8 + SHAPE FOLLOWPIN ( 0 420 ) ( 3952 420 ) + NEW metal1 8 + SHAPE FOLLOWPIN ( 0 140 ) ( 3952 140 ) + NEW metal3 0 + SHAPE STRIPE ( 3150 980 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 3150 980 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 3150 980 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 3150 700 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 3150 700 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 3150 700 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 3150 420 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 3150 420 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 3150 420 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 3150 140 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 3150 140 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 3150 140 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 2250 980 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 2250 980 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 2250 980 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 2250 700 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 2250 700 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 2250 700 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 2250 420 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 2250 420 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 2250 420 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 2250 140 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 2250 140 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 2250 140 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 1350 980 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 1350 980 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 1350 980 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 1350 700 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 1350 700 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 1350 700 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 1350 420 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 1350 420 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 1350 420 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 1350 140 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 1350 140 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 1350 140 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 450 980 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 450 980 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 450 980 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 450 700 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 450 700 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 450 700 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 450 420 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 450 420 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 450 420 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 450 140 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 450 140 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 450 140 ) via1_2_280_160_1_1_300_300 ; + - VSS ( PIN VSS ) ( tapcell.cell4_7 VSS ) ( tapcell.cell4_6 VSS ) ( tapcell.cell4_5 VSS ) ( tapcell.cell4_4 VSS ) ( tapcell.cell4_3 VSS ) ( tapcell.cell4_2 VSS ) + ( tapcell.cell4_1 VSS ) ( tapcell.cell4_0 VSS ) ( tapcell.cell3_7 VSS ) ( tapcell.cell3_6 VSS ) ( tapcell.cell3_5 VSS ) ( tapcell.cell3_4 VSS ) ( tapcell.cell3_3 VSS ) ( tapcell.cell3_2 VSS ) + ( tapcell.cell3_1 VSS ) ( tapcell.cell3_0 VSS ) ( tapcell.cell2_7 VSS ) ( tapcell.cell2_6 VSS ) ( tapcell.cell2_5 VSS ) ( tapcell.cell2_4 VSS ) ( tapcell.cell2_3 VSS ) ( tapcell.cell2_2 VSS ) + ( tapcell.cell2_1 VSS ) ( tapcell.cell2_0 VSS ) ( tapcell.cell1_7 VSS ) ( tapcell.cell1_6 VSS ) ( tapcell.cell1_5 VSS ) ( tapcell.cell1_4 VSS ) ( tapcell.cell1_3 VSS ) ( tapcell.cell1_2 VSS ) + ( tapcell.cell1_1 VSS ) ( tapcell.cell1_0 VSS ) ( tapcell.cell0_7 VSS ) ( tapcell.cell0_6 VSS ) ( tapcell.cell0_5 VSS ) ( tapcell.cell0_4 VSS ) ( tapcell.cell0_3 VSS ) ( tapcell.cell0_2 VSS ) + ( tapcell.cell0_1 VSS ) ( tapcell.cell0_0 VSS ) ( decoder.inv_0 VSS ) ( decoder.inv_1 VSS ) ( decoder.inv_2 VSS ) ( buffer.in[6] VSS ) ( buffer.in[5] VSS ) ( buffer.in[4] VSS ) + ( buffer.in[3] VSS ) ( buffer.in[2] VSS ) ( buffer.in[1] VSS ) ( buffer.in[0] VSS ) ( storage_6_0.select_inv_0 VSS ) ( storage_6_0.gcand VSS ) ( storage_6_0.cg VSS ) ( storage_6_0.bit6.obuf0 VSS ) + ( storage_6_0.bit6.bit VSS ) ( storage_6_0.bit5.obuf0 VSS ) ( storage_6_0.bit5.bit VSS ) ( storage_6_0.bit4.obuf0 VSS ) ( storage_6_0.bit4.bit VSS ) ( storage_6_0.bit3.obuf0 VSS ) ( storage_6_0.bit3.bit VSS ) ( storage_6_0.bit2.obuf0 VSS ) + ( storage_6_0.bit2.bit VSS ) ( storage_6_0.bit1.obuf0 VSS ) ( storage_6_0.bit1.bit VSS ) ( storage_6_0.bit0.obuf0 VSS ) ( storage_6_0.bit0.bit VSS ) ( storage_5_0.select_inv_0 VSS ) ( storage_5_0.gcand VSS ) ( storage_5_0.cg VSS ) + ( storage_5_0.bit6.obuf0 VSS ) ( storage_5_0.bit6.bit VSS ) ( storage_5_0.bit5.obuf0 VSS ) ( storage_5_0.bit5.bit VSS ) ( storage_5_0.bit4.obuf0 VSS ) ( storage_5_0.bit4.bit VSS ) ( storage_5_0.bit3.obuf0 VSS ) ( storage_5_0.bit3.bit VSS ) + ( storage_5_0.bit2.obuf0 VSS ) ( storage_5_0.bit2.bit VSS ) ( storage_5_0.bit1.obuf0 VSS ) ( storage_5_0.bit1.bit VSS ) ( storage_5_0.bit0.obuf0 VSS ) ( storage_5_0.bit0.bit VSS ) ( storage_4_0.select_inv_0 VSS ) ( storage_4_0.gcand VSS ) + ( storage_4_0.cg VSS ) ( storage_4_0.bit6.obuf0 VSS ) ( storage_4_0.bit6.bit VSS ) ( storage_4_0.bit5.obuf0 VSS ) ( storage_4_0.bit5.bit VSS ) ( storage_4_0.bit4.obuf0 VSS ) ( storage_4_0.bit4.bit VSS ) ( storage_4_0.bit3.obuf0 VSS ) + ( storage_4_0.bit3.bit VSS ) ( storage_4_0.bit2.obuf0 VSS ) ( storage_4_0.bit2.bit VSS ) ( storage_4_0.bit1.obuf0 VSS ) ( storage_4_0.bit1.bit VSS ) ( storage_4_0.bit0.obuf0 VSS ) ( storage_4_0.bit0.bit VSS ) ( storage_3_0.select_inv_0 VSS ) + ( storage_3_0.gcand VSS ) ( storage_3_0.cg VSS ) ( storage_3_0.bit6.obuf0 VSS ) ( storage_3_0.bit6.bit VSS ) ( storage_3_0.bit5.obuf0 VSS ) ( storage_3_0.bit5.bit VSS ) ( storage_3_0.bit4.obuf0 VSS ) ( storage_3_0.bit4.bit VSS ) + ( storage_3_0.bit3.obuf0 VSS ) ( storage_3_0.bit3.bit VSS ) ( storage_3_0.bit2.obuf0 VSS ) ( storage_3_0.bit2.bit VSS ) ( storage_3_0.bit1.obuf0 VSS ) ( storage_3_0.bit1.bit VSS ) ( storage_3_0.bit0.obuf0 VSS ) ( storage_3_0.bit0.bit VSS ) + ( storage_2_0.select_inv_0 VSS ) ( storage_2_0.gcand VSS ) ( storage_2_0.cg VSS ) ( storage_2_0.bit6.obuf0 VSS ) ( storage_2_0.bit6.bit VSS ) ( storage_2_0.bit5.obuf0 VSS ) ( storage_2_0.bit5.bit VSS ) ( storage_2_0.bit4.obuf0 VSS ) + ( storage_2_0.bit4.bit VSS ) ( storage_2_0.bit3.obuf0 VSS ) ( storage_2_0.bit3.bit VSS ) ( storage_2_0.bit2.obuf0 VSS ) ( storage_2_0.bit2.bit VSS ) ( storage_2_0.bit1.obuf0 VSS ) ( storage_2_0.bit1.bit VSS ) ( storage_2_0.bit0.obuf0 VSS ) + ( storage_2_0.bit0.bit VSS ) ( storage_1_0.select_inv_0 VSS ) ( storage_1_0.gcand VSS ) ( storage_1_0.cg VSS ) ( storage_1_0.bit6.obuf0 VSS ) ( storage_1_0.bit6.bit VSS ) ( storage_1_0.bit5.obuf0 VSS ) ( storage_1_0.bit5.bit VSS ) + ( storage_1_0.bit4.obuf0 VSS ) ( storage_1_0.bit4.bit VSS ) ( storage_1_0.bit3.obuf0 VSS ) ( storage_1_0.bit3.bit VSS ) ( storage_1_0.bit2.obuf0 VSS ) ( storage_1_0.bit2.bit VSS ) ( storage_1_0.bit1.obuf0 VSS ) ( storage_1_0.bit1.bit VSS ) + ( storage_1_0.bit0.obuf0 VSS ) ( storage_1_0.bit0.bit VSS ) ( storage_0_0.select_inv_0 VSS ) ( storage_0_0.gcand VSS ) ( storage_0_0.cg VSS ) ( storage_0_0.bit6.obuf0 VSS ) ( storage_0_0.bit6.bit VSS ) ( storage_0_0.bit5.obuf0 VSS ) + ( storage_0_0.bit5.bit VSS ) ( storage_0_0.bit4.obuf0 VSS ) ( storage_0_0.bit4.bit VSS ) ( storage_0_0.bit3.obuf0 VSS ) ( storage_0_0.bit3.bit VSS ) ( storage_0_0.bit2.obuf0 VSS ) ( storage_0_0.bit2.bit VSS ) ( storage_0_0.bit1.obuf0 VSS ) + ( storage_0_0.bit1.bit VSS ) ( storage_0_0.bit0.obuf0 VSS ) ( storage_0_0.bit0.bit VSS ) ( decoder_6.buf_port0 VSS ) ( decoder_6.and_layer0 VSS ) ( decoder_5.buf_port0 VSS ) ( decoder_5.and_layer0 VSS ) ( decoder_4.buf_port0 VSS ) + ( decoder_4.and_layer0 VSS ) ( decoder_3.buf_port0 VSS ) ( decoder_3.and_layer0 VSS ) ( decoder_2.buf_port0 VSS ) ( decoder_2.and_layer0 VSS ) ( decoder_1.buf_port0 VSS ) ( decoder_1.and_layer0 VSS ) ( decoder_0.buf_port0 VSS ) + ( decoder_0.and_layer0 VSS ) + USE GROUND + + ROUTED metal4 14 + SHAPE STRIPE ( 3600 -7 ) ( 3600 1127 ) + NEW metal4 14 + SHAPE STRIPE ( 2700 -7 ) ( 2700 1127 ) + NEW metal4 14 + SHAPE STRIPE ( 1800 -7 ) ( 1800 1127 ) + NEW metal4 14 + SHAPE STRIPE ( 900 -7 ) ( 900 1127 ) + NEW metal1 8 + SHAPE FOLLOWPIN ( 0 1120 ) ( 3952 1120 ) + NEW metal1 8 + SHAPE FOLLOWPIN ( 0 840 ) ( 3952 840 ) + NEW metal1 8 + SHAPE FOLLOWPIN ( 0 560 ) ( 3952 560 ) + NEW metal1 8 + SHAPE FOLLOWPIN ( 0 280 ) ( 3952 280 ) + NEW metal1 8 + SHAPE FOLLOWPIN ( 0 0 ) ( 3952 0 ) + NEW metal3 0 + SHAPE STRIPE ( 3600 1120 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 3600 1120 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 3600 1120 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 3600 840 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 3600 840 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 3600 840 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 3600 560 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 3600 560 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 3600 560 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 3600 280 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 3600 280 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 3600 280 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 3600 0 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 3600 0 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 3600 0 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 2700 1120 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 2700 1120 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 2700 1120 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 2700 840 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 2700 840 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 2700 840 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 2700 560 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 2700 560 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 2700 560 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 2700 280 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 2700 280 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 2700 280 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 2700 0 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 2700 0 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 2700 0 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 1800 1120 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 1800 1120 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 1800 1120 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 1800 840 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 1800 840 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 1800 840 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 1800 560 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 1800 560 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 1800 560 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 1800 280 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 1800 280 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 1800 280 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 1800 0 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 1800 0 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 1800 0 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 900 1120 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 900 1120 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 900 1120 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 900 840 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 900 840 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 900 840 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 900 560 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 900 560 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 900 560 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 900 280 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 900 280 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 900 280 ) via1_2_280_160_1_1_300_300 + NEW metal3 0 + SHAPE STRIPE ( 900 0 ) via3_4_280_160_1_1_320_320 + NEW metal2 0 + SHAPE STRIPE ( 900 0 ) via2_3_280_160_1_1_320_320 + NEW metal1 0 + SHAPE STRIPE ( 900 0 ) via1_2_280_160_1_1_300_300 ; +END SPECIALNETS +NETS 120 ; + - D[0] ( PIN D[0] ) ( buffer.in[0] A ) + USE SIGNAL + + ROUTED metal4 ( 121 1057 ) ( * 1113 0 ) + NEW metal3 ( 28 1057 ) ( 121 * ) + NEW metal3 ( 121 1057 ) via3_2 + NEW metal1 ( 28 1057 ) via1_4 + NEW metal2 ( 28 1057 ) via2_5 ; + - D[1] ( PIN D[1] ) ( buffer.in[1] A ) + USE SIGNAL + + ROUTED metal4 ( 513 1057 ) ( * 1113 0 ) + NEW metal3 ( 503 1057 ) ( 513 * ) + NEW metal3 ( 513 1057 ) via3_2 + NEW metal1 ( 503 1057 ) via1_4 + NEW metal2 ( 503 1057 ) via2_5 ; + - D[2] ( PIN D[2] ) ( buffer.in[2] A ) + USE SIGNAL + + ROUTED metal4 ( 1017 1057 ) ( * 1113 0 ) + NEW metal3 ( 997 1057 ) ( 1017 * ) + NEW metal3 ( 1017 1057 ) via3_2 + NEW metal1 ( 997 1057 ) via1_4 + NEW metal2 ( 997 1057 ) via2_5 ; + - D[3] ( PIN D[3] ) ( buffer.in[3] A ) + USE SIGNAL + + ROUTED metal4 ( 1465 1057 ) ( * 1113 0 ) + NEW metal3 ( 1465 1057 ) ( 1472 * ) + NEW metal3 ( 1465 1057 ) via3_2 + NEW metal1 ( 1472 1057 ) via1_4 + NEW metal2 ( 1472 1057 ) via2_5 ; + - D[4] ( PIN D[4] ) ( buffer.in[4] A ) + USE SIGNAL + + ROUTED metal4 ( 1969 1057 ) ( * 1113 0 ) + NEW metal3 ( 1966 1057 ) ( 1969 * ) + NEW metal3 ( 1969 1057 ) via3_2 + NEW metal1 ( 1966 1057 ) via1_4 + NEW metal2 ( 1966 1057 ) via2_5 ; + - D[5] ( PIN D[5] ) ( buffer.in[5] A ) + USE SIGNAL + + ROUTED metal4 ( 2417 1057 ) ( * 1113 0 ) + NEW metal3 ( 2417 1057 ) ( 2441 * ) + NEW metal3 ( 2417 1057 ) via3_2 + NEW metal1 ( 2441 1057 ) via1_4 + NEW metal2 ( 2441 1057 ) via2_5 ; + - D[6] ( PIN D[6] ) ( buffer.in[6] A ) + USE SIGNAL + + ROUTED metal4 ( 2921 1057 ) ( * 1113 0 ) + NEW metal3 ( 2921 1057 ) ( 2935 * ) + NEW metal3 ( 2921 1057 ) via3_2 + NEW metal1 ( 2935 1057 ) via1_4 + NEW metal2 ( 2935 1057 ) via2_5 ; + - D_nets[0].net ( buffer.in[0] Z ) ( storage_6_0.bit0.bit D ) ( storage_5_0.bit0.bit D ) ( storage_4_0.bit0.bit D ) ( storage_3_0.bit0.bit D ) ( storage_2_0.bit0.bit D ) ( storage_1_0.bit0.bit D ) + ( storage_0_0.bit0.bit D ) + USE SIGNAL + + ROUTED metal2 ( 104 903 ) ( * 1001 ) + NEW metal2 ( 66 1001 ) ( 104 * ) + NEW metal2 ( 104 777 ) ( * 903 ) + NEW metal2 ( 104 623 ) ( * 777 ) + NEW metal2 ( 104 497 ) ( * 623 ) + NEW metal2 ( 104 343 ) ( * 497 ) + NEW metal2 ( 104 217 ) ( * 343 ) + NEW metal2 ( 104 63 ) ( * 217 ) + NEW metal1 ( 104 903 ) via1_4 + NEW metal1 ( 66 1001 ) via1_7 + NEW metal1 ( 104 777 ) via1_4 + NEW metal1 ( 104 623 ) via1_4 + NEW metal1 ( 104 497 ) via1_4 + NEW metal1 ( 104 343 ) via1_4 + NEW metal1 ( 104 217 ) via1_4 + NEW metal1 ( 104 63 ) via1_4 ; + - D_nets[1].net ( buffer.in[1] Z ) ( storage_6_0.bit1.bit D ) ( storage_5_0.bit1.bit D ) ( storage_4_0.bit1.bit D ) ( storage_3_0.bit1.bit D ) ( storage_2_0.bit1.bit D ) ( storage_1_0.bit1.bit D ) + ( storage_0_0.bit1.bit D ) + USE SIGNAL + + ROUTED metal2 ( 579 903 ) ( * 1001 ) + NEW metal2 ( 541 1001 ) ( 579 * ) + NEW metal2 ( 579 777 ) ( * 903 ) + NEW metal2 ( 579 623 ) ( * 777 ) + NEW metal2 ( 579 497 ) ( * 623 ) + NEW metal2 ( 579 343 ) ( * 497 ) + NEW metal2 ( 579 217 ) ( * 343 ) + NEW metal2 ( 579 63 ) ( * 217 ) + NEW metal1 ( 579 903 ) via1_4 + NEW metal1 ( 541 1001 ) via1_7 + NEW metal1 ( 579 777 ) via1_4 + NEW metal1 ( 579 623 ) via1_4 + NEW metal1 ( 579 497 ) via1_4 + NEW metal1 ( 579 343 ) via1_4 + NEW metal1 ( 579 217 ) via1_4 + NEW metal1 ( 579 63 ) via1_4 ; + - D_nets[2].net ( buffer.in[2] Z ) ( storage_6_0.bit2.bit D ) ( storage_5_0.bit2.bit D ) ( storage_4_0.bit2.bit D ) ( storage_3_0.bit2.bit D ) ( storage_2_0.bit2.bit D ) ( storage_1_0.bit2.bit D ) + ( storage_0_0.bit2.bit D ) + USE SIGNAL + + ROUTED metal2 ( 1073 903 ) ( * 1001 ) + NEW metal2 ( 1035 1001 ) ( 1073 * ) + NEW metal2 ( 1073 777 ) ( * 903 ) + NEW metal2 ( 1073 623 ) ( * 777 ) + NEW metal2 ( 1073 497 ) ( * 623 ) + NEW metal2 ( 1073 343 ) ( * 497 ) + NEW metal2 ( 1073 217 ) ( * 343 ) + NEW metal2 ( 1073 63 ) ( * 217 ) + NEW metal1 ( 1073 903 ) via1_4 + NEW metal1 ( 1035 1001 ) via1_7 + NEW metal1 ( 1073 777 ) via1_4 + NEW metal1 ( 1073 623 ) via1_4 + NEW metal1 ( 1073 497 ) via1_4 + NEW metal1 ( 1073 343 ) via1_4 + NEW metal1 ( 1073 217 ) via1_4 + NEW metal1 ( 1073 63 ) via1_4 ; + - D_nets[3].net ( buffer.in[3] Z ) ( storage_6_0.bit3.bit D ) ( storage_5_0.bit3.bit D ) ( storage_4_0.bit3.bit D ) ( storage_3_0.bit3.bit D ) ( storage_2_0.bit3.bit D ) ( storage_1_0.bit3.bit D ) + ( storage_0_0.bit3.bit D ) + USE SIGNAL + + ROUTED metal2 ( 1548 903 ) ( * 1001 ) + NEW metal2 ( 1510 1001 ) ( 1548 * ) + NEW metal2 ( 1548 777 ) ( * 903 ) + NEW metal2 ( 1548 623 ) ( * 777 ) + NEW metal2 ( 1548 497 ) ( * 623 ) + NEW metal2 ( 1548 343 ) ( * 497 ) + NEW metal2 ( 1548 217 ) ( * 343 ) + NEW metal2 ( 1548 63 ) ( * 217 ) + NEW metal1 ( 1548 903 ) via1_4 + NEW metal1 ( 1510 1001 ) via1_7 + NEW metal1 ( 1548 777 ) via1_4 + NEW metal1 ( 1548 623 ) via1_4 + NEW metal1 ( 1548 497 ) via1_4 + NEW metal1 ( 1548 343 ) via1_4 + NEW metal1 ( 1548 217 ) via1_4 + NEW metal1 ( 1548 63 ) via1_4 ; + - D_nets[4].net ( buffer.in[4] Z ) ( storage_6_0.bit4.bit D ) ( storage_5_0.bit4.bit D ) ( storage_4_0.bit4.bit D ) ( storage_3_0.bit4.bit D ) ( storage_2_0.bit4.bit D ) ( storage_1_0.bit4.bit D ) + ( storage_0_0.bit4.bit D ) + USE SIGNAL + + ROUTED metal2 ( 2042 903 ) ( * 1001 ) + NEW metal2 ( 2004 1001 ) ( 2042 * ) + NEW metal2 ( 2042 777 ) ( * 903 ) + NEW metal2 ( 2042 623 ) ( * 777 ) + NEW metal2 ( 2042 497 ) ( * 623 ) + NEW metal2 ( 2042 343 ) ( * 497 ) + NEW metal2 ( 2042 217 ) ( * 343 ) + NEW metal2 ( 2042 63 ) ( * 217 ) + NEW metal1 ( 2042 903 ) via1_4 + NEW metal1 ( 2004 1001 ) via1_7 + NEW metal1 ( 2042 777 ) via1_4 + NEW metal1 ( 2042 623 ) via1_4 + NEW metal1 ( 2042 497 ) via1_4 + NEW metal1 ( 2042 343 ) via1_4 + NEW metal1 ( 2042 217 ) via1_4 + NEW metal1 ( 2042 63 ) via1_4 ; + - D_nets[5].net ( buffer.in[5] Z ) ( storage_6_0.bit5.bit D ) ( storage_5_0.bit5.bit D ) ( storage_4_0.bit5.bit D ) ( storage_3_0.bit5.bit D ) ( storage_2_0.bit5.bit D ) ( storage_1_0.bit5.bit D ) + ( storage_0_0.bit5.bit D ) + USE SIGNAL + + ROUTED metal2 ( 2517 903 ) ( * 1001 ) + NEW metal2 ( 2479 1001 ) ( 2517 * ) + NEW metal2 ( 2517 777 ) ( * 903 ) + NEW metal2 ( 2517 623 ) ( * 777 ) + NEW metal2 ( 2517 497 ) ( * 623 ) + NEW metal2 ( 2517 343 ) ( * 497 ) + NEW metal2 ( 2517 217 ) ( * 343 ) + NEW metal2 ( 2517 63 ) ( * 217 ) + NEW metal1 ( 2517 903 ) via1_4 + NEW metal1 ( 2479 1001 ) via1_7 + NEW metal1 ( 2517 777 ) via1_4 + NEW metal1 ( 2517 623 ) via1_4 + NEW metal1 ( 2517 497 ) via1_4 + NEW metal1 ( 2517 343 ) via1_4 + NEW metal1 ( 2517 217 ) via1_4 + NEW metal1 ( 2517 63 ) via1_4 ; + - D_nets[6].net ( buffer.in[6] Z ) ( storage_6_0.bit6.bit D ) ( storage_5_0.bit6.bit D ) ( storage_4_0.bit6.bit D ) ( storage_3_0.bit6.bit D ) ( storage_2_0.bit6.bit D ) ( storage_1_0.bit6.bit D ) + ( storage_0_0.bit6.bit D ) + USE SIGNAL + + ROUTED metal2 ( 3011 903 ) ( * 1001 ) + NEW metal2 ( 2973 1001 ) ( 3011 * ) + NEW metal2 ( 3011 777 ) ( * 903 ) + NEW metal2 ( 3011 623 ) ( * 777 ) + NEW metal2 ( 3011 497 ) ( * 623 ) + NEW metal2 ( 3011 343 ) ( * 497 ) + NEW metal2 ( 3011 217 ) ( * 343 ) + NEW metal2 ( 3011 63 ) ( * 217 ) + NEW metal1 ( 3011 903 ) via1_4 + NEW metal1 ( 2973 1001 ) via1_7 + NEW metal1 ( 3011 777 ) via1_4 + NEW metal1 ( 3011 623 ) via1_4 + NEW metal1 ( 3011 497 ) via1_4 + NEW metal1 ( 3011 343 ) via1_4 + NEW metal1 ( 3011 217 ) via1_4 + NEW metal1 ( 3011 63 ) via1_4 ; + - Q[0] ( PIN Q[0] ) ( storage_6_0.bit0.obuf0 Z ) ( storage_5_0.bit0.obuf0 Z ) ( storage_4_0.bit0.obuf0 Z ) ( storage_3_0.bit0.obuf0 Z ) ( storage_2_0.bit0.obuf0 Z ) ( storage_1_0.bit0.obuf0 Z ) + ( storage_0_0.bit0.obuf0 Z ) + USE SIGNAL + + ROUTED metal3 ( 345 945 ) ( 351 * ) + NEW metal4 ( 345 945 ) ( * 1113 0 ) + NEW metal2 ( 351 805 ) ( * 875 ) + NEW metal2 ( 351 665 ) ( * 735 ) + NEW metal2 ( 351 525 ) ( * 595 ) + NEW metal2 ( 351 385 ) ( * 455 ) + NEW metal2 ( 351 245 ) ( * 315 ) + NEW metal2 ( 351 105 ) ( * 175 ) + NEW metal1 ( 351 945 ) via1_4 + NEW metal2 ( 351 945 ) via2_5 + NEW metal3 ( 345 945 ) via3_2 + NEW metal1 ( 351 805 ) via1_4 + NEW metal1 ( 351 875 ) via1_4 + NEW metal1 ( 351 665 ) via1_4 + NEW metal1 ( 351 735 ) via1_4 + NEW metal1 ( 351 525 ) via1_4 + NEW metal1 ( 351 595 ) via1_4 + NEW metal1 ( 351 385 ) via1_4 + NEW metal1 ( 351 455 ) via1_4 + NEW metal1 ( 351 245 ) via1_4 + NEW metal1 ( 351 315 ) via1_4 + NEW metal1 ( 351 105 ) via1_4 + NEW metal1 ( 351 175 ) via1_4 ; + - Q[1] ( PIN Q[1] ) ( storage_6_0.bit1.obuf0 Z ) ( storage_5_0.bit1.obuf0 Z ) ( storage_4_0.bit1.obuf0 Z ) ( storage_3_0.bit1.obuf0 Z ) ( storage_2_0.bit1.obuf0 Z ) ( storage_1_0.bit1.obuf0 Z ) + ( storage_0_0.bit1.obuf0 Z ) + USE SIGNAL + + ROUTED metal3 ( 826 945 ) ( 849 * ) + NEW metal4 ( 849 945 ) ( * 1113 0 ) + NEW metal2 ( 826 805 ) ( * 945 ) + NEW metal2 ( 826 665 ) ( * 805 ) + NEW metal2 ( 826 525 ) ( * 665 ) + NEW metal2 ( 826 385 ) ( * 525 ) + NEW metal2 ( 826 245 ) ( * 385 ) + NEW metal2 ( 826 105 ) ( * 245 ) + NEW metal1 ( 826 945 ) via1_4 + NEW metal2 ( 826 945 ) via2_5 + NEW metal3 ( 849 945 ) via3_2 + NEW metal1 ( 826 805 ) via1_4 + NEW metal1 ( 826 665 ) via1_4 + NEW metal1 ( 826 525 ) via1_4 + NEW metal1 ( 826 385 ) via1_4 + NEW metal1 ( 826 245 ) via1_4 + NEW metal1 ( 826 105 ) via1_4 ; + - Q[2] ( PIN Q[2] ) ( storage_6_0.bit2.obuf0 Z ) ( storage_5_0.bit2.obuf0 Z ) ( storage_4_0.bit2.obuf0 Z ) ( storage_3_0.bit2.obuf0 Z ) ( storage_2_0.bit2.obuf0 Z ) ( storage_1_0.bit2.obuf0 Z ) + ( storage_0_0.bit2.obuf0 Z ) + USE SIGNAL + + ROUTED metal3 ( 1297 945 ) ( 1320 * ) + NEW metal4 ( 1297 945 ) ( * 1113 0 ) + NEW metal2 ( 1320 805 ) ( * 875 ) + NEW metal2 ( 1320 665 ) ( * 735 ) + NEW metal2 ( 1320 525 ) ( * 595 ) + NEW metal2 ( 1320 385 ) ( * 455 ) + NEW metal2 ( 1320 245 ) ( * 315 ) + NEW metal2 ( 1320 105 ) ( * 175 ) + NEW metal1 ( 1320 945 ) via1_4 + NEW metal2 ( 1320 945 ) via2_5 + NEW metal3 ( 1297 945 ) via3_2 + NEW metal1 ( 1320 805 ) via1_4 + NEW metal1 ( 1320 875 ) via1_4 + NEW metal1 ( 1320 665 ) via1_4 + NEW metal1 ( 1320 735 ) via1_4 + NEW metal1 ( 1320 525 ) via1_4 + NEW metal1 ( 1320 595 ) via1_4 + NEW metal1 ( 1320 385 ) via1_4 + NEW metal1 ( 1320 455 ) via1_4 + NEW metal1 ( 1320 245 ) via1_4 + NEW metal1 ( 1320 315 ) via1_4 + NEW metal1 ( 1320 105 ) via1_4 + NEW metal1 ( 1320 175 ) via1_4 ; + - Q[3] ( PIN Q[3] ) ( storage_6_0.bit3.obuf0 Z ) ( storage_5_0.bit3.obuf0 Z ) ( storage_4_0.bit3.obuf0 Z ) ( storage_3_0.bit3.obuf0 Z ) ( storage_2_0.bit3.obuf0 Z ) ( storage_1_0.bit3.obuf0 Z ) + ( storage_0_0.bit3.obuf0 Z ) + USE SIGNAL + + ROUTED metal3 ( 1745 945 ) ( 1795 * ) + NEW metal4 ( 1745 945 ) ( * 1113 0 ) + NEW metal2 ( 1776 805 ) ( 1795 * ) + NEW metal2 ( 1776 805 ) ( * 875 ) + NEW metal2 ( 1776 875 ) ( 1795 * ) + NEW metal2 ( 1795 665 ) ( * 735 ) + NEW metal2 ( 1776 525 ) ( 1795 * ) + NEW metal2 ( 1776 525 ) ( * 595 ) + NEW metal2 ( 1776 595 ) ( 1795 * ) + NEW metal2 ( 1795 385 ) ( * 455 ) + NEW metal2 ( 1776 245 ) ( 1795 * ) + NEW metal2 ( 1776 245 ) ( * 315 ) + NEW metal2 ( 1776 315 ) ( 1795 * ) + NEW metal2 ( 1795 105 ) ( * 175 ) + NEW metal1 ( 1795 945 ) via1_4 + NEW metal2 ( 1795 945 ) via2_5 + NEW metal3 ( 1745 945 ) via3_2 + NEW metal1 ( 1795 805 ) via1_4 + NEW metal1 ( 1795 875 ) via1_4 + NEW metal1 ( 1795 665 ) via1_4 + NEW metal1 ( 1795 735 ) via1_4 + NEW metal1 ( 1795 525 ) via1_4 + NEW metal1 ( 1795 595 ) via1_4 + NEW metal1 ( 1795 385 ) via1_4 + NEW metal1 ( 1795 455 ) via1_4 + NEW metal1 ( 1795 245 ) via1_4 + NEW metal1 ( 1795 315 ) via1_4 + NEW metal1 ( 1795 105 ) via1_4 + NEW metal1 ( 1795 175 ) via1_4 ; + - Q[4] ( PIN Q[4] ) ( storage_6_0.bit4.obuf0 Z ) ( storage_5_0.bit4.obuf0 Z ) ( storage_4_0.bit4.obuf0 Z ) ( storage_3_0.bit4.obuf0 Z ) ( storage_2_0.bit4.obuf0 Z ) ( storage_1_0.bit4.obuf0 Z ) + ( storage_0_0.bit4.obuf0 Z ) + USE SIGNAL + + ROUTED metal3 ( 2289 945 ) ( 2305 * ) + NEW metal4 ( 2305 945 ) ( * 1113 0 ) + NEW metal2 ( 2289 805 ) ( * 945 ) + NEW metal2 ( 2289 665 ) ( * 805 ) + NEW metal2 ( 2289 525 ) ( * 665 ) + NEW metal2 ( 2289 385 ) ( * 525 ) + NEW metal2 ( 2289 245 ) ( * 385 ) + NEW metal2 ( 2289 105 ) ( * 245 ) + NEW metal1 ( 2289 945 ) via1_4 + NEW metal2 ( 2289 945 ) via2_5 + NEW metal3 ( 2305 945 ) via3_2 + NEW metal1 ( 2289 805 ) via1_4 + NEW metal1 ( 2289 665 ) via1_4 + NEW metal1 ( 2289 525 ) via1_4 + NEW metal1 ( 2289 385 ) via1_4 + NEW metal1 ( 2289 245 ) via1_4 + NEW metal1 ( 2289 105 ) via1_4 ; + - Q[5] ( PIN Q[5] ) ( storage_6_0.bit5.obuf0 Z ) ( storage_5_0.bit5.obuf0 Z ) ( storage_4_0.bit5.obuf0 Z ) ( storage_3_0.bit5.obuf0 Z ) ( storage_2_0.bit5.obuf0 Z ) ( storage_1_0.bit5.obuf0 Z ) + ( storage_0_0.bit5.obuf0 Z ) + USE SIGNAL + + ROUTED metal3 ( 2753 945 ) ( 2764 * ) + NEW metal4 ( 2753 945 ) ( * 1113 0 ) + NEW metal2 ( 2764 805 ) ( * 875 ) + NEW metal2 ( 2764 665 ) ( * 735 ) + NEW metal2 ( 2764 525 ) ( * 595 ) + NEW metal2 ( 2764 385 ) ( * 455 ) + NEW metal2 ( 2764 245 ) ( * 315 ) + NEW metal2 ( 2764 105 ) ( * 175 ) + NEW metal1 ( 2764 945 ) via1_4 + NEW metal2 ( 2764 945 ) via2_5 + NEW metal3 ( 2753 945 ) via3_2 + NEW metal1 ( 2764 805 ) via1_4 + NEW metal1 ( 2764 875 ) via1_4 + NEW metal1 ( 2764 665 ) via1_4 + NEW metal1 ( 2764 735 ) via1_4 + NEW metal1 ( 2764 525 ) via1_4 + NEW metal1 ( 2764 595 ) via1_4 + NEW metal1 ( 2764 385 ) via1_4 + NEW metal1 ( 2764 455 ) via1_4 + NEW metal1 ( 2764 245 ) via1_4 + NEW metal1 ( 2764 315 ) via1_4 + NEW metal1 ( 2764 105 ) via1_4 + NEW metal1 ( 2764 175 ) via1_4 ; + - Q[6] ( PIN Q[6] ) ( storage_6_0.bit6.obuf0 Z ) ( storage_5_0.bit6.obuf0 Z ) ( storage_4_0.bit6.obuf0 Z ) ( storage_3_0.bit6.obuf0 Z ) ( storage_2_0.bit6.obuf0 Z ) ( storage_1_0.bit6.obuf0 Z ) + ( storage_0_0.bit6.obuf0 Z ) + USE SIGNAL + + ROUTED metal3 ( 3257 945 ) ( 3258 * ) + NEW metal4 ( 3257 945 ) ( * 1113 0 ) + NEW metal2 ( 3258 805 ) ( * 875 ) + NEW metal2 ( 3258 665 ) ( * 735 ) + NEW metal2 ( 3258 525 ) ( * 595 ) + NEW metal2 ( 3258 385 ) ( * 455 ) + NEW metal2 ( 3258 245 ) ( * 315 ) + NEW metal2 ( 3258 105 ) ( * 175 ) + NEW metal1 ( 3258 945 ) via1_4 + NEW metal2 ( 3258 945 ) via2_5 + NEW metal3 ( 3257 945 ) via3_2 + NEW metal1 ( 3258 805 ) via1_4 + NEW metal1 ( 3258 875 ) via1_4 + NEW metal1 ( 3258 665 ) via1_4 + NEW metal1 ( 3258 735 ) via1_4 + NEW metal1 ( 3258 525 ) via1_4 + NEW metal1 ( 3258 595 ) via1_4 + NEW metal1 ( 3258 385 ) via1_4 + NEW metal1 ( 3258 455 ) via1_4 + NEW metal1 ( 3258 245 ) via1_4 + NEW metal1 ( 3258 315 ) via1_4 + NEW metal1 ( 3258 105 ) via1_4 + NEW metal1 ( 3258 175 ) via1_4 ; + - addr[0] ( PIN addr[0] ) ( decoder.inv_0 A ) ( decoder_5.and_layer0 A1 ) ( decoder_3.and_layer0 A1 ) ( decoder_1.and_layer0 A1 ) + USE SIGNAL + + ROUTED metal2 ( 3771 217 ) ( * 231 ) + NEW metal3 ( 3771 231 ) ( 3948 * 0 ) + NEW metal2 ( 3771 441 ) ( * 497 ) + NEW metal2 ( 3695 441 ) ( 3771 * ) + NEW metal2 ( 3695 231 ) ( * 441 ) + NEW metal3 ( 3695 231 ) ( 3771 * ) + NEW metal2 ( 3771 735 ) ( * 777 ) + NEW metal3 ( 3695 735 ) ( 3771 * ) + NEW metal2 ( 3695 441 ) ( * 735 ) + NEW metal2 ( 3923 735 ) ( * 903 ) + NEW metal3 ( 3771 735 ) ( 3923 * ) + NEW metal1 ( 3771 217 ) via1_4 + NEW metal2 ( 3771 231 ) via2_5 + NEW metal1 ( 3771 497 ) via1_4 + NEW metal2 ( 3695 231 ) via2_5 + NEW metal1 ( 3771 777 ) via1_4 + NEW metal2 ( 3771 735 ) via2_5 + NEW metal2 ( 3695 735 ) via2_5 + NEW metal1 ( 3923 903 ) via1_4 + NEW metal2 ( 3923 735 ) via2_5 ; + - addr[1] ( PIN addr[1] ) ( decoder.inv_1 A ) ( decoder_6.and_layer0 A2 ) ( decoder_3.and_layer0 A2 ) ( decoder_2.and_layer0 A2 ) + USE SIGNAL + + ROUTED metal2 ( 3790 497 ) ( * 553 ) + NEW metal2 ( 3790 553 ) ( 3809 * ) + NEW metal2 ( 3809 553 ) ( * 791 ) + NEW metal2 ( 3796 791 ) ( 3809 * ) + NEW metal2 ( 3796 791 ) ( * 805 ) + NEW metal2 ( 3790 805 ) ( 3796 * ) + NEW metal2 ( 3790 805 ) ( * 903 ) + NEW metal2 ( 3923 483 ) ( * 497 ) + NEW metal3 ( 3790 483 ) ( 3923 * ) + NEW metal2 ( 3790 483 ) ( * 497 ) + NEW metal2 ( 3790 343 ) ( * 357 ) + NEW metal2 ( 3790 357 ) ( 3793 * ) + NEW metal2 ( 3793 357 ) ( * 385 ) + NEW metal2 ( 3790 385 ) ( 3793 * ) + NEW metal2 ( 3790 385 ) ( * 483 ) + NEW metal3 ( 3790 343 ) ( 3948 * 0 ) + NEW metal1 ( 3790 497 ) via1_4 + NEW metal1 ( 3790 903 ) via1_4 + NEW metal1 ( 3923 497 ) via1_4 + NEW metal2 ( 3923 483 ) via2_5 + NEW metal2 ( 3790 483 ) via2_5 + NEW metal1 ( 3790 343 ) via1_4 + NEW metal2 ( 3790 343 ) via2_5 ; + - addr[2] ( PIN addr[2] ) ( decoder.inv_2 A ) + USE SIGNAL + + ROUTED metal3 ( 3923 119 ) ( 3948 * 0 ) + NEW metal2 ( 3923 63 ) ( * 119 ) + NEW metal2 ( 3923 119 ) via2_5 + NEW metal1 ( 3923 63 ) via1_4 ; + - clk ( PIN clk ) ( storage_6_0.cg CK ) ( storage_5_0.cg CK ) ( storage_4_0.cg CK ) ( storage_3_0.cg CK ) ( storage_2_0.cg CK ) ( storage_1_0.cg CK ) + ( storage_0_0.cg CK ) + USE SIGNAL + + ROUTED metal2 ( 3581 147 ) ( * 231 ) + NEW metal3 ( 3581 147 ) ( 3948 * 0 ) + NEW metal2 ( 3581 49 ) ( * 147 ) + NEW metal2 ( 3581 231 ) ( * 329 ) + NEW metal2 ( 3581 329 ) ( * 511 ) + NEW metal2 ( 3581 511 ) ( * 609 ) + NEW metal2 ( 3581 609 ) ( * 791 ) + NEW metal2 ( 3581 791 ) ( * 889 ) + NEW metal1 ( 3581 231 ) via1_7 + NEW metal2 ( 3581 147 ) via2_5 + NEW metal1 ( 3581 49 ) via1_7 + NEW metal1 ( 3581 329 ) via1_7 + NEW metal1 ( 3581 511 ) via1_7 + NEW metal1 ( 3581 609 ) via1_7 + NEW metal1 ( 3581 791 ) via1_7 + NEW metal1 ( 3581 889 ) via1_7 ; + - decoder_0.decoder0 ( storage_0_0.select_inv_0 A ) ( storage_0_0.gcand A1 ) ( decoder_0.buf_port0 Z ) + USE SIGNAL + + ROUTED metal2 ( 3733 49 ) ( * 63 ) + NEW metal3 ( 3733 49 ) ( 3885 * ) + NEW metal2 ( 3657 35 ) ( * 63 ) + NEW metal2 ( 3657 35 ) ( 3733 * ) + NEW metal2 ( 3733 35 ) ( * 49 ) + NEW metal1 ( 3733 63 ) via1_4 + NEW metal2 ( 3733 49 ) via2_5 + NEW metal1 ( 3885 49 ) via1_4 + NEW metal2 ( 3885 49 ) via2_5 + NEW metal1 ( 3657 63 ) via1_4 ; + - decoder_0.decoder_out ( decoder_0.buf_port0 A ) ( decoder_0.and_layer0 ZN ) + USE SIGNAL + + ROUTED metal2 ( 3828 63 ) ( 3847 * ) + NEW metal1 ( 3847 63 ) via1_4 + NEW metal1 ( 3828 63 ) via1_4 ; + - decoder_0.layer_in0 + USE SIGNAL ; + - decoder_1.decoder0 ( storage_1_0.select_inv_0 A ) ( storage_1_0.gcand A1 ) ( decoder_1.buf_port0 Z ) + USE SIGNAL + + ROUTED metal2 ( 3733 203 ) ( * 217 ) + NEW metal3 ( 3733 203 ) ( 3885 * ) + NEW metal2 ( 3657 203 ) ( * 217 ) + NEW metal3 ( 3657 203 ) ( 3733 * ) + NEW metal1 ( 3733 217 ) via1_4 + NEW metal2 ( 3733 203 ) via2_5 + NEW metal1 ( 3885 203 ) via1_4 + NEW metal2 ( 3885 203 ) via2_5 + NEW metal1 ( 3657 217 ) via1_4 + NEW metal2 ( 3657 203 ) via2_5 ; + - decoder_1.decoder_out ( decoder_1.buf_port0 A ) ( decoder_1.and_layer0 ZN ) + USE SIGNAL + + ROUTED metal2 ( 3828 217 ) ( 3847 * ) + NEW metal1 ( 3847 217 ) via1_4 + NEW metal1 ( 3828 217 ) via1_4 ; + - decoder_1.layer_in0 + USE SIGNAL ; + - decoder_2.decoder0 ( storage_2_0.select_inv_0 A ) ( storage_2_0.gcand A1 ) ( decoder_2.buf_port0 Z ) + USE SIGNAL + + ROUTED metal2 ( 3733 329 ) ( * 343 ) + NEW metal3 ( 3733 329 ) ( 3885 * ) + NEW metal2 ( 3657 315 ) ( * 343 ) + NEW metal3 ( 3657 315 ) ( 3733 * ) + NEW metal3 ( 3733 315 ) ( * 329 ) + NEW metal1 ( 3733 343 ) via1_4 + NEW metal2 ( 3733 329 ) via2_5 + NEW metal1 ( 3885 329 ) via1_4 + NEW metal2 ( 3885 329 ) via2_5 + NEW metal1 ( 3657 343 ) via1_4 + NEW metal2 ( 3657 315 ) via2_5 ; + - decoder_2.decoder_out ( decoder_2.buf_port0 A ) ( decoder_2.and_layer0 ZN ) + USE SIGNAL + + ROUTED metal2 ( 3828 343 ) ( 3847 * ) + NEW metal1 ( 3847 343 ) via1_4 + NEW metal1 ( 3828 343 ) via1_4 ; + - decoder_2.layer_in0 + USE SIGNAL ; + - decoder_3.decoder0 ( storage_3_0.select_inv_0 A ) ( storage_3_0.gcand A1 ) ( decoder_3.buf_port0 Z ) + USE SIGNAL + + ROUTED metal2 ( 3733 497 ) ( 3752 * ) + NEW metal3 ( 3752 497 ) ( 3885 * ) + NEW metal2 ( 3657 483 ) ( * 497 ) + NEW metal3 ( 3657 483 ) ( 3733 * ) + NEW metal3 ( 3733 483 ) ( * 497 ) + NEW metal3 ( 3733 497 ) ( 3752 * ) + NEW metal1 ( 3733 497 ) via1_4 + NEW metal2 ( 3752 497 ) via2_5 + NEW metal1 ( 3885 497 ) via1_4 + NEW metal2 ( 3885 497 ) via2_5 + NEW metal1 ( 3657 497 ) via1_4 + NEW metal2 ( 3657 483 ) via2_5 ; + - decoder_3.decoder_out ( decoder_3.buf_port0 A ) ( decoder_3.and_layer0 ZN ) + USE SIGNAL + + ROUTED metal2 ( 3828 497 ) ( 3847 * ) + NEW metal1 ( 3847 497 ) via1_4 + NEW metal1 ( 3828 497 ) via1_4 ; + - decoder_3.layer_in0 + USE SIGNAL ; + - decoder_4.decoder0 ( storage_4_0.select_inv_0 A ) ( storage_4_0.gcand A1 ) ( decoder_4.buf_port0 Z ) + USE SIGNAL + + ROUTED metal2 ( 3733 609 ) ( * 623 ) + NEW metal3 ( 3733 609 ) ( 3885 * ) + NEW metal2 ( 3657 595 ) ( * 623 ) + NEW metal3 ( 3657 595 ) ( 3733 * ) + NEW metal3 ( 3733 595 ) ( * 609 ) + NEW metal1 ( 3733 623 ) via1_4 + NEW metal2 ( 3733 609 ) via2_5 + NEW metal1 ( 3885 609 ) via1_4 + NEW metal2 ( 3885 609 ) via2_5 + NEW metal1 ( 3657 623 ) via1_4 + NEW metal2 ( 3657 595 ) via2_5 ; + - decoder_4.decoder_out ( decoder_4.buf_port0 A ) ( decoder_4.and_layer0 ZN ) + USE SIGNAL + + ROUTED metal2 ( 3828 623 ) ( 3847 * ) + NEW metal1 ( 3847 623 ) via1_4 + NEW metal1 ( 3828 623 ) via1_4 ; + - decoder_4.layer_in0 + USE SIGNAL ; + - decoder_5.decoder0 ( storage_5_0.select_inv_0 A ) ( storage_5_0.gcand A1 ) ( decoder_5.buf_port0 Z ) + USE SIGNAL + + ROUTED metal2 ( 3733 777 ) ( * 791 ) + NEW metal3 ( 3733 791 ) ( 3885 * ) + NEW metal2 ( 3657 777 ) ( * 805 ) + NEW metal3 ( 3657 805 ) ( 3677 * ) + NEW metal3 ( 3677 791 ) ( * 805 ) + NEW metal3 ( 3677 791 ) ( 3733 * ) + NEW metal1 ( 3733 777 ) via1_4 + NEW metal2 ( 3733 791 ) via2_5 + NEW metal1 ( 3885 791 ) via1_4 + NEW metal2 ( 3885 791 ) via2_5 + NEW metal1 ( 3657 777 ) via1_4 + NEW metal2 ( 3657 805 ) via2_5 ; + - decoder_5.decoder_out ( decoder_5.buf_port0 A ) ( decoder_5.and_layer0 ZN ) + USE SIGNAL + + ROUTED metal2 ( 3828 777 ) ( 3847 * ) + NEW metal1 ( 3847 777 ) via1_4 + NEW metal1 ( 3828 777 ) via1_4 ; + - decoder_5.layer_in0 + USE SIGNAL ; + - decoder_6.decoder0 ( storage_6_0.select_inv_0 A ) ( storage_6_0.gcand A1 ) ( decoder_6.buf_port0 Z ) + USE SIGNAL + + ROUTED metal2 ( 3733 903 ) ( * 931 ) + NEW metal2 ( 3733 931 ) ( 3885 * ) + NEW metal2 ( 3657 903 ) ( * 931 ) + NEW metal2 ( 3657 931 ) ( 3733 * ) + NEW metal1 ( 3733 903 ) via1_4 + NEW metal1 ( 3885 931 ) via1_4 + NEW metal1 ( 3657 903 ) via1_4 ; + - decoder_6.decoder_out ( decoder_6.buf_port0 A ) ( decoder_6.and_layer0 ZN ) + USE SIGNAL + + ROUTED metal2 ( 3828 903 ) ( 3847 * ) + NEW metal1 ( 3847 903 ) via1_4 + NEW metal1 ( 3828 903 ) via1_4 ; + - decoder_6.layer_in0 + USE SIGNAL ; + - inv.addr[0] ( decoder.inv_0 ZN ) ( decoder_6.and_layer0 A1 ) ( decoder_4.and_layer0 A1 ) ( decoder_2.and_layer0 A1 ) ( decoder_0.and_layer0 A1 ) + USE SIGNAL + + ROUTED metal2 ( 3771 889 ) ( * 903 ) + NEW metal3 ( 3771 889 ) ( 3942 * ) + NEW metal2 ( 3771 623 ) ( * 637 ) + NEW metal3 ( 3771 637 ) ( 3866 * ) + NEW metal2 ( 3866 637 ) ( * 889 ) + NEW metal2 ( 3771 315 ) ( * 336 ) + NEW metal2 ( 3771 315 ) ( 3866 * ) + NEW metal2 ( 3866 315 ) ( * 637 ) + NEW metal2 ( 3771 63 ) ( * 105 ) + NEW metal3 ( 3771 105 ) ( 3809 * ) + NEW metal2 ( 3809 105 ) ( * 315 ) + NEW metal1 ( 3771 903 ) via1_4 + NEW metal2 ( 3771 889 ) via2_5 + NEW metal1 ( 3942 889 ) via1_4 + NEW metal2 ( 3942 889 ) via2_5 + NEW metal1 ( 3771 623 ) via1_4 + NEW metal2 ( 3771 637 ) via2_5 + NEW metal2 ( 3866 637 ) via2_5 + NEW metal2 ( 3866 889 ) via2_5 + NEW metal1 ( 3771 336 ) via1_7 + NEW metal1 ( 3771 63 ) via1_4 + NEW metal2 ( 3771 105 ) via2_5 + NEW metal2 ( 3809 105 ) via2_5 ; + - inv.addr[1] ( decoder.inv_1 ZN ) ( decoder_5.and_layer0 A2 ) ( decoder_4.and_layer0 A2 ) ( decoder_1.and_layer0 A2 ) ( decoder_0.and_layer0 A2 ) + USE SIGNAL + + ROUTED metal2 ( 3790 63 ) ( * 217 ) + NEW metal2 ( 3942 217 ) ( * 441 ) + NEW metal3 ( 3790 217 ) ( 3942 * ) + NEW metal3 ( 3790 623 ) ( 3942 * ) + NEW metal2 ( 3942 539 ) ( * 623 ) + NEW metal2 ( 3790 623 ) ( * 770 ) + NEW metal1 ( 3790 217 ) via1_4 + NEW metal1 ( 3790 63 ) via1_4 + NEW metal1 ( 3942 441 ) via1_7 + NEW metal2 ( 3942 217 ) via2_5 + NEW metal2 ( 3790 217 ) via2_5 + NEW metal1 ( 3790 623 ) via1_4 + NEW metal2 ( 3790 623 ) via2_5 + NEW metal2 ( 3942 623 ) via2_5 + NEW metal1 ( 3942 539 ) via1_7 + NEW metal1 ( 3790 770 ) via1_4 ; + - inv.addr[2] ( decoder.inv_2 ZN ) + USE SIGNAL ; + - storage_0_0.bit0.storage ( storage_0_0.bit0.obuf0 A ) ( storage_0_0.bit0.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 294 63 ) ( 427 * ) + NEW metal1 ( 294 63 ) via1_4 + NEW metal1 ( 427 63 ) via1_4 ; + - storage_0_0.bit1.storage ( storage_0_0.bit1.obuf0 A ) ( storage_0_0.bit1.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 769 63 ) ( 902 * ) + NEW metal1 ( 769 63 ) via1_4 + NEW metal2 ( 769 63 ) via2_5 + NEW metal1 ( 902 63 ) via1_4 + NEW metal2 ( 902 63 ) via2_5 ; + - storage_0_0.bit2.storage ( storage_0_0.bit2.obuf0 A ) ( storage_0_0.bit2.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1263 63 ) ( 1396 * ) + NEW metal1 ( 1263 63 ) via1_4 + NEW metal1 ( 1396 63 ) via1_4 ; + - storage_0_0.bit3.storage ( storage_0_0.bit3.obuf0 A ) ( storage_0_0.bit3.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1738 63 ) ( 1871 * ) + NEW metal1 ( 1738 63 ) via1_4 + NEW metal1 ( 1871 63 ) via1_4 ; + - storage_0_0.bit4.storage ( storage_0_0.bit4.obuf0 A ) ( storage_0_0.bit4.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 2232 63 ) ( 2365 * ) + NEW metal1 ( 2232 63 ) via1_4 + NEW metal2 ( 2232 63 ) via2_5 + NEW metal1 ( 2365 63 ) via1_4 + NEW metal2 ( 2365 63 ) via2_5 ; + - storage_0_0.bit5.storage ( storage_0_0.bit5.obuf0 A ) ( storage_0_0.bit5.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 2707 63 ) ( 2840 * ) + NEW metal1 ( 2707 63 ) via1_4 + NEW metal1 ( 2840 63 ) via1_4 ; + - storage_0_0.bit6.storage ( storage_0_0.bit6.obuf0 A ) ( storage_0_0.bit6.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 3201 63 ) ( 3334 * ) + NEW metal1 ( 3201 63 ) via1_4 + NEW metal1 ( 3334 63 ) via1_4 ; + - storage_0_0.gclock ( storage_0_0.cg GCK ) ( storage_0_0.bit6.bit CK ) ( storage_0_0.bit5.bit CK ) ( storage_0_0.bit4.bit CK ) ( storage_0_0.bit3.bit CK ) ( storage_0_0.bit2.bit CK ) ( storage_0_0.bit1.bit CK ) + ( storage_0_0.bit0.bit CK ) + USE SIGNAL + + ROUTED metal3 ( 180 63 ) ( 655 * ) + NEW metal2 ( 1149 49 ) ( * 63 ) + NEW metal3 ( 737 49 ) ( 1149 * ) + NEW metal3 ( 737 49 ) ( * 63 ) + NEW metal3 ( 655 63 ) ( 737 * ) + NEW metal2 ( 3087 49 ) ( * 63 ) + NEW metal2 ( 2593 49 ) ( * 63 ) + NEW metal3 ( 2593 49 ) ( 3087 * ) + NEW metal2 ( 2118 49 ) ( * 63 ) + NEW metal3 ( 2118 49 ) ( 2593 * ) + NEW metal2 ( 1624 49 ) ( * 63 ) + NEW metal3 ( 1624 49 ) ( 2118 * ) + NEW metal3 ( 1149 49 ) ( 1624 * ) + NEW metal3 ( 3087 49 ) ( 3638 * ) + NEW metal1 ( 655 63 ) via1_4 + NEW metal2 ( 655 63 ) via2_5 + NEW metal1 ( 180 63 ) via1_4 + NEW metal2 ( 180 63 ) via2_5 + NEW metal1 ( 1149 63 ) via1_4 + NEW metal2 ( 1149 49 ) via2_5 + NEW metal1 ( 3638 49 ) via1_4 + NEW metal2 ( 3638 49 ) via2_5 + NEW metal1 ( 3087 63 ) via1_4 + NEW metal2 ( 3087 49 ) via2_5 + NEW metal1 ( 2593 63 ) via1_4 + NEW metal2 ( 2593 49 ) via2_5 + NEW metal1 ( 2118 63 ) via1_4 + NEW metal2 ( 2118 49 ) via2_5 + NEW metal1 ( 1624 63 ) via1_4 + NEW metal2 ( 1624 49 ) via2_5 ; + - storage_0_0.select0_b ( storage_0_0.select_inv_0 ZN ) ( storage_0_0.bit6.obuf0 EN ) ( storage_0_0.bit5.obuf0 EN ) ( storage_0_0.bit4.obuf0 EN ) ( storage_0_0.bit3.obuf0 EN ) ( storage_0_0.bit2.obuf0 EN ) ( storage_0_0.bit1.obuf0 EN ) + ( storage_0_0.bit0.obuf0 EN ) + USE SIGNAL + + ROUTED metal3 ( 465 77 ) ( 940 * ) + NEW metal3 ( 3733 63 ) ( * 77 ) + NEW metal3 ( 3733 63 ) ( 3752 * ) + NEW metal3 ( 2878 77 ) ( 3372 * ) + NEW metal3 ( 2403 77 ) ( 2878 * ) + NEW metal3 ( 1909 77 ) ( 2403 * ) + NEW metal3 ( 1434 77 ) ( 1909 * ) + NEW metal3 ( 940 77 ) ( 1434 * ) + NEW metal3 ( 3372 77 ) ( 3733 * ) + NEW metal1 ( 940 77 ) via1_4 + NEW metal2 ( 940 77 ) via2_5 + NEW metal1 ( 465 77 ) via1_4 + NEW metal2 ( 465 77 ) via2_5 + NEW metal1 ( 3752 63 ) via1_4 + NEW metal2 ( 3752 63 ) via2_5 + NEW metal1 ( 3372 77 ) via1_4 + NEW metal2 ( 3372 77 ) via2_5 + NEW metal1 ( 2878 77 ) via1_4 + NEW metal2 ( 2878 77 ) via2_5 + NEW metal1 ( 2403 77 ) via1_4 + NEW metal2 ( 2403 77 ) via2_5 + NEW metal1 ( 1909 77 ) via1_4 + NEW metal2 ( 1909 77 ) via2_5 + NEW metal1 ( 1434 77 ) via1_4 + NEW metal2 ( 1434 77 ) via2_5 ; + - storage_0_0.we0 ( storage_0_0.gcand ZN ) ( storage_0_0.cg E ) + USE SIGNAL + + ROUTED metal3 ( 3505 63 ) ( 3714 * ) + NEW metal1 ( 3505 63 ) via1_4 + NEW metal2 ( 3505 63 ) via2_5 + NEW metal1 ( 3714 63 ) via1_4 + NEW metal2 ( 3714 63 ) via2_5 ; + - storage_1_0.bit0.storage ( storage_1_0.bit0.obuf0 A ) ( storage_1_0.bit0.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 294 217 ) ( 427 * ) + NEW metal1 ( 427 217 ) via1_4 + NEW metal1 ( 294 217 ) via1_4 ; + - storage_1_0.bit1.storage ( storage_1_0.bit1.obuf0 A ) ( storage_1_0.bit1.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 769 217 ) ( 902 * ) + NEW metal1 ( 902 217 ) via1_4 + NEW metal2 ( 902 217 ) via2_5 + NEW metal1 ( 769 217 ) via1_4 + NEW metal2 ( 769 217 ) via2_5 ; + - storage_1_0.bit2.storage ( storage_1_0.bit2.obuf0 A ) ( storage_1_0.bit2.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1263 217 ) ( 1396 * ) + NEW metal1 ( 1396 217 ) via1_4 + NEW metal1 ( 1263 217 ) via1_4 ; + - storage_1_0.bit3.storage ( storage_1_0.bit3.obuf0 A ) ( storage_1_0.bit3.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1738 217 ) ( 1871 * ) + NEW metal1 ( 1871 217 ) via1_4 + NEW metal1 ( 1738 217 ) via1_4 ; + - storage_1_0.bit4.storage ( storage_1_0.bit4.obuf0 A ) ( storage_1_0.bit4.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 2232 217 ) ( 2365 * ) + NEW metal1 ( 2365 217 ) via1_4 + NEW metal2 ( 2365 217 ) via2_5 + NEW metal1 ( 2232 217 ) via1_4 + NEW metal2 ( 2232 217 ) via2_5 ; + - storage_1_0.bit5.storage ( storage_1_0.bit5.obuf0 A ) ( storage_1_0.bit5.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 2707 217 ) ( 2840 * ) + NEW metal1 ( 2840 217 ) via1_4 + NEW metal1 ( 2707 217 ) via1_4 ; + - storage_1_0.bit6.storage ( storage_1_0.bit6.obuf0 A ) ( storage_1_0.bit6.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 3201 217 ) ( 3334 * ) + NEW metal1 ( 3334 217 ) via1_4 + NEW metal1 ( 3201 217 ) via1_4 ; + - storage_1_0.gclock ( storage_1_0.cg GCK ) ( storage_1_0.bit6.bit CK ) ( storage_1_0.bit5.bit CK ) ( storage_1_0.bit4.bit CK ) ( storage_1_0.bit3.bit CK ) ( storage_1_0.bit2.bit CK ) ( storage_1_0.bit1.bit CK ) + ( storage_1_0.bit0.bit CK ) + USE SIGNAL + + ROUTED metal3 ( 180 217 ) ( 655 * ) + NEW metal2 ( 1149 217 ) ( * 231 ) + NEW metal3 ( 737 231 ) ( 1149 * ) + NEW metal3 ( 737 217 ) ( * 231 ) + NEW metal3 ( 655 217 ) ( 737 * ) + NEW metal2 ( 3087 217 ) ( * 231 ) + NEW metal2 ( 2593 217 ) ( * 231 ) + NEW metal3 ( 2593 231 ) ( 3087 * ) + NEW metal2 ( 2118 217 ) ( * 231 ) + NEW metal3 ( 2118 231 ) ( 2593 * ) + NEW metal2 ( 1624 217 ) ( * 231 ) + NEW metal3 ( 1624 231 ) ( 2118 * ) + NEW metal3 ( 1149 231 ) ( 1624 * ) + NEW metal3 ( 3087 231 ) ( 3638 * ) + NEW metal1 ( 655 217 ) via1_4 + NEW metal2 ( 655 217 ) via2_5 + NEW metal1 ( 180 217 ) via1_4 + NEW metal2 ( 180 217 ) via2_5 + NEW metal1 ( 1149 217 ) via1_4 + NEW metal2 ( 1149 231 ) via2_5 + NEW metal1 ( 3638 231 ) via1_4 + NEW metal2 ( 3638 231 ) via2_5 + NEW metal1 ( 3087 217 ) via1_4 + NEW metal2 ( 3087 231 ) via2_5 + NEW metal1 ( 2593 217 ) via1_4 + NEW metal2 ( 2593 231 ) via2_5 + NEW metal1 ( 2118 217 ) via1_4 + NEW metal2 ( 2118 231 ) via2_5 + NEW metal1 ( 1624 217 ) via1_4 + NEW metal2 ( 1624 231 ) via2_5 ; + - storage_1_0.select0_b ( storage_1_0.select_inv_0 ZN ) ( storage_1_0.bit6.obuf0 EN ) ( storage_1_0.bit5.obuf0 EN ) ( storage_1_0.bit4.obuf0 EN ) ( storage_1_0.bit3.obuf0 EN ) ( storage_1_0.bit2.obuf0 EN ) ( storage_1_0.bit1.obuf0 EN ) + ( storage_1_0.bit0.obuf0 EN ) + USE SIGNAL + + ROUTED metal3 ( 465 189 ) ( 940 * ) + NEW metal3 ( 2878 189 ) ( 3372 * ) + NEW metal3 ( 2403 189 ) ( 2878 * ) + NEW metal3 ( 1909 189 ) ( 2403 * ) + NEW metal3 ( 1434 189 ) ( 1909 * ) + NEW metal3 ( 940 189 ) ( 1434 * ) + NEW metal3 ( 3372 189 ) ( 3752 * ) + NEW metal1 ( 940 189 ) via1_4 + NEW metal2 ( 940 189 ) via2_5 + NEW metal1 ( 465 189 ) via1_4 + NEW metal2 ( 465 189 ) via2_5 + NEW metal1 ( 3752 189 ) via1_4 + NEW metal2 ( 3752 189 ) via2_5 + NEW metal1 ( 3372 189 ) via1_4 + NEW metal2 ( 3372 189 ) via2_5 + NEW metal1 ( 2878 189 ) via1_4 + NEW metal2 ( 2878 189 ) via2_5 + NEW metal1 ( 2403 189 ) via1_4 + NEW metal2 ( 2403 189 ) via2_5 + NEW metal1 ( 1909 189 ) via1_4 + NEW metal2 ( 1909 189 ) via2_5 + NEW metal1 ( 1434 189 ) via1_4 + NEW metal2 ( 1434 189 ) via2_5 ; + - storage_1_0.we0 ( storage_1_0.gcand ZN ) ( storage_1_0.cg E ) + USE SIGNAL + + ROUTED metal3 ( 3505 217 ) ( 3714 * ) + NEW metal1 ( 3505 217 ) via1_4 + NEW metal2 ( 3505 217 ) via2_5 + NEW metal1 ( 3714 217 ) via1_4 + NEW metal2 ( 3714 217 ) via2_5 ; + - storage_2_0.bit0.storage ( storage_2_0.bit0.obuf0 A ) ( storage_2_0.bit0.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 294 343 ) ( 427 * ) + NEW metal1 ( 294 343 ) via1_4 + NEW metal1 ( 427 343 ) via1_4 ; + - storage_2_0.bit1.storage ( storage_2_0.bit1.obuf0 A ) ( storage_2_0.bit1.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 769 343 ) ( 902 * ) + NEW metal1 ( 769 343 ) via1_4 + NEW metal2 ( 769 343 ) via2_5 + NEW metal1 ( 902 343 ) via1_4 + NEW metal2 ( 902 343 ) via2_5 ; + - storage_2_0.bit2.storage ( storage_2_0.bit2.obuf0 A ) ( storage_2_0.bit2.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1263 343 ) ( 1396 * ) + NEW metal1 ( 1263 343 ) via1_4 + NEW metal1 ( 1396 343 ) via1_4 ; + - storage_2_0.bit3.storage ( storage_2_0.bit3.obuf0 A ) ( storage_2_0.bit3.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1738 343 ) ( 1871 * ) + NEW metal1 ( 1738 343 ) via1_4 + NEW metal1 ( 1871 343 ) via1_4 ; + - storage_2_0.bit4.storage ( storage_2_0.bit4.obuf0 A ) ( storage_2_0.bit4.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 2232 343 ) ( 2365 * ) + NEW metal1 ( 2232 343 ) via1_4 + NEW metal2 ( 2232 343 ) via2_5 + NEW metal1 ( 2365 343 ) via1_4 + NEW metal2 ( 2365 343 ) via2_5 ; + - storage_2_0.bit5.storage ( storage_2_0.bit5.obuf0 A ) ( storage_2_0.bit5.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 2707 343 ) ( 2840 * ) + NEW metal1 ( 2707 343 ) via1_4 + NEW metal1 ( 2840 343 ) via1_4 ; + - storage_2_0.bit6.storage ( storage_2_0.bit6.obuf0 A ) ( storage_2_0.bit6.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 3201 343 ) ( 3334 * ) + NEW metal1 ( 3201 343 ) via1_4 + NEW metal1 ( 3334 343 ) via1_4 ; + - storage_2_0.gclock ( storage_2_0.cg GCK ) ( storage_2_0.bit6.bit CK ) ( storage_2_0.bit5.bit CK ) ( storage_2_0.bit4.bit CK ) ( storage_2_0.bit3.bit CK ) ( storage_2_0.bit2.bit CK ) ( storage_2_0.bit1.bit CK ) + ( storage_2_0.bit0.bit CK ) + USE SIGNAL + + ROUTED metal3 ( 180 343 ) ( 655 * ) + NEW metal2 ( 1149 329 ) ( * 343 ) + NEW metal3 ( 737 329 ) ( 1149 * ) + NEW metal3 ( 737 329 ) ( * 343 ) + NEW metal3 ( 655 343 ) ( 737 * ) + NEW metal2 ( 3087 329 ) ( * 343 ) + NEW metal2 ( 2593 329 ) ( * 343 ) + NEW metal3 ( 2593 329 ) ( 3087 * ) + NEW metal2 ( 2118 329 ) ( * 343 ) + NEW metal3 ( 2118 329 ) ( 2593 * ) + NEW metal2 ( 1624 329 ) ( * 343 ) + NEW metal3 ( 1624 329 ) ( 2118 * ) + NEW metal3 ( 1149 329 ) ( 1624 * ) + NEW metal3 ( 3087 329 ) ( 3638 * ) + NEW metal1 ( 655 343 ) via1_4 + NEW metal2 ( 655 343 ) via2_5 + NEW metal1 ( 180 343 ) via1_4 + NEW metal2 ( 180 343 ) via2_5 + NEW metal1 ( 1149 343 ) via1_4 + NEW metal2 ( 1149 329 ) via2_5 + NEW metal1 ( 3638 329 ) via1_4 + NEW metal2 ( 3638 329 ) via2_5 + NEW metal1 ( 3087 343 ) via1_4 + NEW metal2 ( 3087 329 ) via2_5 + NEW metal1 ( 2593 343 ) via1_4 + NEW metal2 ( 2593 329 ) via2_5 + NEW metal1 ( 2118 343 ) via1_4 + NEW metal2 ( 2118 329 ) via2_5 + NEW metal1 ( 1624 343 ) via1_4 + NEW metal2 ( 1624 329 ) via2_5 ; + - storage_2_0.select0_b ( storage_2_0.select_inv_0 ZN ) ( storage_2_0.bit6.obuf0 EN ) ( storage_2_0.bit5.obuf0 EN ) ( storage_2_0.bit4.obuf0 EN ) ( storage_2_0.bit3.obuf0 EN ) ( storage_2_0.bit2.obuf0 EN ) ( storage_2_0.bit1.obuf0 EN ) + ( storage_2_0.bit0.obuf0 EN ) + USE SIGNAL + + ROUTED metal3 ( 465 357 ) ( 940 * ) + NEW metal3 ( 3733 343 ) ( * 357 ) + NEW metal3 ( 3733 343 ) ( 3752 * ) + NEW metal3 ( 2878 357 ) ( 3372 * ) + NEW metal3 ( 2403 357 ) ( 2878 * ) + NEW metal3 ( 1909 357 ) ( 2403 * ) + NEW metal3 ( 1434 357 ) ( 1909 * ) + NEW metal3 ( 940 357 ) ( 1434 * ) + NEW metal3 ( 3372 357 ) ( 3733 * ) + NEW metal1 ( 940 357 ) via1_4 + NEW metal2 ( 940 357 ) via2_5 + NEW metal1 ( 465 357 ) via1_4 + NEW metal2 ( 465 357 ) via2_5 + NEW metal1 ( 3752 343 ) via1_4 + NEW metal2 ( 3752 343 ) via2_5 + NEW metal1 ( 3372 357 ) via1_4 + NEW metal2 ( 3372 357 ) via2_5 + NEW metal1 ( 2878 357 ) via1_4 + NEW metal2 ( 2878 357 ) via2_5 + NEW metal1 ( 2403 357 ) via1_4 + NEW metal2 ( 2403 357 ) via2_5 + NEW metal1 ( 1909 357 ) via1_4 + NEW metal2 ( 1909 357 ) via2_5 + NEW metal1 ( 1434 357 ) via1_4 + NEW metal2 ( 1434 357 ) via2_5 ; + - storage_2_0.we0 ( storage_2_0.gcand ZN ) ( storage_2_0.cg E ) + USE SIGNAL + + ROUTED metal3 ( 3505 343 ) ( 3714 * ) + NEW metal1 ( 3505 343 ) via1_4 + NEW metal2 ( 3505 343 ) via2_5 + NEW metal1 ( 3714 343 ) via1_4 + NEW metal2 ( 3714 343 ) via2_5 ; + - storage_3_0.bit0.storage ( storage_3_0.bit0.obuf0 A ) ( storage_3_0.bit0.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 294 497 ) ( 427 * ) + NEW metal1 ( 427 497 ) via1_4 + NEW metal1 ( 294 497 ) via1_4 ; + - storage_3_0.bit1.storage ( storage_3_0.bit1.obuf0 A ) ( storage_3_0.bit1.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 769 497 ) ( 902 * ) + NEW metal1 ( 902 497 ) via1_4 + NEW metal2 ( 902 497 ) via2_5 + NEW metal1 ( 769 497 ) via1_4 + NEW metal2 ( 769 497 ) via2_5 ; + - storage_3_0.bit2.storage ( storage_3_0.bit2.obuf0 A ) ( storage_3_0.bit2.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1263 497 ) ( 1396 * ) + NEW metal1 ( 1396 497 ) via1_4 + NEW metal1 ( 1263 497 ) via1_4 ; + - storage_3_0.bit3.storage ( storage_3_0.bit3.obuf0 A ) ( storage_3_0.bit3.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1738 497 ) ( 1871 * ) + NEW metal1 ( 1871 497 ) via1_4 + NEW metal1 ( 1738 497 ) via1_4 ; + - storage_3_0.bit4.storage ( storage_3_0.bit4.obuf0 A ) ( storage_3_0.bit4.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 2232 497 ) ( 2365 * ) + NEW metal1 ( 2365 497 ) via1_4 + NEW metal2 ( 2365 497 ) via2_5 + NEW metal1 ( 2232 497 ) via1_4 + NEW metal2 ( 2232 497 ) via2_5 ; + - storage_3_0.bit5.storage ( storage_3_0.bit5.obuf0 A ) ( storage_3_0.bit5.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 2707 497 ) ( 2840 * ) + NEW metal1 ( 2840 497 ) via1_4 + NEW metal1 ( 2707 497 ) via1_4 ; + - storage_3_0.bit6.storage ( storage_3_0.bit6.obuf0 A ) ( storage_3_0.bit6.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 3201 497 ) ( 3334 * ) + NEW metal1 ( 3334 497 ) via1_4 + NEW metal1 ( 3201 497 ) via1_4 ; + - storage_3_0.gclock ( storage_3_0.cg GCK ) ( storage_3_0.bit6.bit CK ) ( storage_3_0.bit5.bit CK ) ( storage_3_0.bit4.bit CK ) ( storage_3_0.bit3.bit CK ) ( storage_3_0.bit2.bit CK ) ( storage_3_0.bit1.bit CK ) + ( storage_3_0.bit0.bit CK ) + USE SIGNAL + + ROUTED metal3 ( 180 497 ) ( 655 * ) + NEW metal2 ( 1149 497 ) ( * 511 ) + NEW metal3 ( 737 511 ) ( 1149 * ) + NEW metal3 ( 737 497 ) ( * 511 ) + NEW metal3 ( 655 497 ) ( 737 * ) + NEW metal2 ( 3087 497 ) ( * 511 ) + NEW metal2 ( 2593 497 ) ( * 511 ) + NEW metal3 ( 2593 511 ) ( 3087 * ) + NEW metal2 ( 2118 497 ) ( * 511 ) + NEW metal3 ( 2118 511 ) ( 2593 * ) + NEW metal2 ( 1624 497 ) ( * 511 ) + NEW metal3 ( 1624 511 ) ( 2118 * ) + NEW metal3 ( 1149 511 ) ( 1624 * ) + NEW metal3 ( 3087 511 ) ( 3638 * ) + NEW metal1 ( 655 497 ) via1_4 + NEW metal2 ( 655 497 ) via2_5 + NEW metal1 ( 180 497 ) via1_4 + NEW metal2 ( 180 497 ) via2_5 + NEW metal1 ( 1149 497 ) via1_4 + NEW metal2 ( 1149 511 ) via2_5 + NEW metal1 ( 3638 511 ) via1_4 + NEW metal2 ( 3638 511 ) via2_5 + NEW metal1 ( 3087 497 ) via1_4 + NEW metal2 ( 3087 511 ) via2_5 + NEW metal1 ( 2593 497 ) via1_4 + NEW metal2 ( 2593 511 ) via2_5 + NEW metal1 ( 2118 497 ) via1_4 + NEW metal2 ( 2118 511 ) via2_5 + NEW metal1 ( 1624 497 ) via1_4 + NEW metal2 ( 1624 511 ) via2_5 ; + - storage_3_0.select0_b ( storage_3_0.select_inv_0 ZN ) ( storage_3_0.bit6.obuf0 EN ) ( storage_3_0.bit5.obuf0 EN ) ( storage_3_0.bit4.obuf0 EN ) ( storage_3_0.bit3.obuf0 EN ) ( storage_3_0.bit2.obuf0 EN ) ( storage_3_0.bit1.obuf0 EN ) + ( storage_3_0.bit0.obuf0 EN ) + USE SIGNAL + + ROUTED metal3 ( 465 469 ) ( 940 * ) + NEW metal3 ( 2878 469 ) ( 3372 * ) + NEW metal3 ( 2403 469 ) ( 2878 * ) + NEW metal3 ( 1909 469 ) ( 2403 * ) + NEW metal3 ( 1434 469 ) ( 1909 * ) + NEW metal3 ( 940 469 ) ( 1434 * ) + NEW metal3 ( 3372 469 ) ( 3752 * ) + NEW metal1 ( 940 469 ) via1_4 + NEW metal2 ( 940 469 ) via2_5 + NEW metal1 ( 465 469 ) via1_4 + NEW metal2 ( 465 469 ) via2_5 + NEW metal1 ( 3752 469 ) via1_4 + NEW metal2 ( 3752 469 ) via2_5 + NEW metal1 ( 3372 469 ) via1_4 + NEW metal2 ( 3372 469 ) via2_5 + NEW metal1 ( 2878 469 ) via1_4 + NEW metal2 ( 2878 469 ) via2_5 + NEW metal1 ( 2403 469 ) via1_4 + NEW metal2 ( 2403 469 ) via2_5 + NEW metal1 ( 1909 469 ) via1_4 + NEW metal2 ( 1909 469 ) via2_5 + NEW metal1 ( 1434 469 ) via1_4 + NEW metal2 ( 1434 469 ) via2_5 ; + - storage_3_0.we0 ( storage_3_0.gcand ZN ) ( storage_3_0.cg E ) + USE SIGNAL + + ROUTED metal3 ( 3505 497 ) ( 3714 * ) + NEW metal1 ( 3505 497 ) via1_4 + NEW metal2 ( 3505 497 ) via2_5 + NEW metal1 ( 3714 497 ) via1_4 + NEW metal2 ( 3714 497 ) via2_5 ; + - storage_4_0.bit0.storage ( storage_4_0.bit0.obuf0 A ) ( storage_4_0.bit0.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 294 623 ) ( 427 * ) + NEW metal1 ( 294 623 ) via1_4 + NEW metal1 ( 427 623 ) via1_4 ; + - storage_4_0.bit1.storage ( storage_4_0.bit1.obuf0 A ) ( storage_4_0.bit1.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 769 623 ) ( 902 * ) + NEW metal1 ( 769 623 ) via1_4 + NEW metal2 ( 769 623 ) via2_5 + NEW metal1 ( 902 623 ) via1_4 + NEW metal2 ( 902 623 ) via2_5 ; + - storage_4_0.bit2.storage ( storage_4_0.bit2.obuf0 A ) ( storage_4_0.bit2.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1263 623 ) ( 1396 * ) + NEW metal1 ( 1263 623 ) via1_4 + NEW metal1 ( 1396 623 ) via1_4 ; + - storage_4_0.bit3.storage ( storage_4_0.bit3.obuf0 A ) ( storage_4_0.bit3.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1738 623 ) ( 1871 * ) + NEW metal1 ( 1738 623 ) via1_4 + NEW metal1 ( 1871 623 ) via1_4 ; + - storage_4_0.bit4.storage ( storage_4_0.bit4.obuf0 A ) ( storage_4_0.bit4.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 2232 623 ) ( 2365 * ) + NEW metal1 ( 2232 623 ) via1_4 + NEW metal2 ( 2232 623 ) via2_5 + NEW metal1 ( 2365 623 ) via1_4 + NEW metal2 ( 2365 623 ) via2_5 ; + - storage_4_0.bit5.storage ( storage_4_0.bit5.obuf0 A ) ( storage_4_0.bit5.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 2707 623 ) ( 2840 * ) + NEW metal1 ( 2707 623 ) via1_4 + NEW metal1 ( 2840 623 ) via1_4 ; + - storage_4_0.bit6.storage ( storage_4_0.bit6.obuf0 A ) ( storage_4_0.bit6.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 3201 623 ) ( 3334 * ) + NEW metal1 ( 3201 623 ) via1_4 + NEW metal1 ( 3334 623 ) via1_4 ; + - storage_4_0.gclock ( storage_4_0.cg GCK ) ( storage_4_0.bit6.bit CK ) ( storage_4_0.bit5.bit CK ) ( storage_4_0.bit4.bit CK ) ( storage_4_0.bit3.bit CK ) ( storage_4_0.bit2.bit CK ) ( storage_4_0.bit1.bit CK ) + ( storage_4_0.bit0.bit CK ) + USE SIGNAL + + ROUTED metal3 ( 180 623 ) ( 655 * ) + NEW metal2 ( 1149 609 ) ( * 623 ) + NEW metal3 ( 737 609 ) ( 1149 * ) + NEW metal3 ( 737 609 ) ( * 623 ) + NEW metal3 ( 655 623 ) ( 737 * ) + NEW metal2 ( 3087 609 ) ( * 623 ) + NEW metal2 ( 2593 609 ) ( * 623 ) + NEW metal3 ( 2593 609 ) ( 3087 * ) + NEW metal2 ( 2118 609 ) ( * 623 ) + NEW metal3 ( 2118 609 ) ( 2593 * ) + NEW metal2 ( 1624 609 ) ( * 623 ) + NEW metal3 ( 1624 609 ) ( 2118 * ) + NEW metal3 ( 1149 609 ) ( 1624 * ) + NEW metal3 ( 3087 609 ) ( 3638 * ) + NEW metal1 ( 655 623 ) via1_4 + NEW metal2 ( 655 623 ) via2_5 + NEW metal1 ( 180 623 ) via1_4 + NEW metal2 ( 180 623 ) via2_5 + NEW metal1 ( 1149 623 ) via1_4 + NEW metal2 ( 1149 609 ) via2_5 + NEW metal1 ( 3638 609 ) via1_4 + NEW metal2 ( 3638 609 ) via2_5 + NEW metal1 ( 3087 623 ) via1_4 + NEW metal2 ( 3087 609 ) via2_5 + NEW metal1 ( 2593 623 ) via1_4 + NEW metal2 ( 2593 609 ) via2_5 + NEW metal1 ( 2118 623 ) via1_4 + NEW metal2 ( 2118 609 ) via2_5 + NEW metal1 ( 1624 623 ) via1_4 + NEW metal2 ( 1624 609 ) via2_5 ; + - storage_4_0.select0_b ( storage_4_0.select_inv_0 ZN ) ( storage_4_0.bit6.obuf0 EN ) ( storage_4_0.bit5.obuf0 EN ) ( storage_4_0.bit4.obuf0 EN ) ( storage_4_0.bit3.obuf0 EN ) ( storage_4_0.bit2.obuf0 EN ) ( storage_4_0.bit1.obuf0 EN ) + ( storage_4_0.bit0.obuf0 EN ) + USE SIGNAL + + ROUTED metal3 ( 465 637 ) ( 940 * ) + NEW metal3 ( 3733 623 ) ( * 637 ) + NEW metal3 ( 3733 623 ) ( 3752 * ) + NEW metal3 ( 2878 637 ) ( 3372 * ) + NEW metal3 ( 2403 637 ) ( 2878 * ) + NEW metal3 ( 1909 637 ) ( 2403 * ) + NEW metal3 ( 1434 637 ) ( 1909 * ) + NEW metal3 ( 940 637 ) ( 1434 * ) + NEW metal3 ( 3372 637 ) ( 3733 * ) + NEW metal1 ( 940 637 ) via1_4 + NEW metal2 ( 940 637 ) via2_5 + NEW metal1 ( 465 637 ) via1_4 + NEW metal2 ( 465 637 ) via2_5 + NEW metal1 ( 3752 623 ) via1_4 + NEW metal2 ( 3752 623 ) via2_5 + NEW metal1 ( 3372 637 ) via1_4 + NEW metal2 ( 3372 637 ) via2_5 + NEW metal1 ( 2878 637 ) via1_4 + NEW metal2 ( 2878 637 ) via2_5 + NEW metal1 ( 2403 637 ) via1_4 + NEW metal2 ( 2403 637 ) via2_5 + NEW metal1 ( 1909 637 ) via1_4 + NEW metal2 ( 1909 637 ) via2_5 + NEW metal1 ( 1434 637 ) via1_4 + NEW metal2 ( 1434 637 ) via2_5 ; + - storage_4_0.we0 ( storage_4_0.gcand ZN ) ( storage_4_0.cg E ) + USE SIGNAL + + ROUTED metal3 ( 3505 623 ) ( 3714 * ) + NEW metal1 ( 3505 623 ) via1_4 + NEW metal2 ( 3505 623 ) via2_5 + NEW metal1 ( 3714 623 ) via1_4 + NEW metal2 ( 3714 623 ) via2_5 ; + - storage_5_0.bit0.storage ( storage_5_0.bit0.obuf0 A ) ( storage_5_0.bit0.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 294 777 ) ( 427 * ) + NEW metal1 ( 427 777 ) via1_4 + NEW metal1 ( 294 777 ) via1_4 ; + - storage_5_0.bit1.storage ( storage_5_0.bit1.obuf0 A ) ( storage_5_0.bit1.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 769 777 ) ( 902 * ) + NEW metal1 ( 902 777 ) via1_4 + NEW metal2 ( 902 777 ) via2_5 + NEW metal1 ( 769 777 ) via1_4 + NEW metal2 ( 769 777 ) via2_5 ; + - storage_5_0.bit2.storage ( storage_5_0.bit2.obuf0 A ) ( storage_5_0.bit2.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1263 777 ) ( 1396 * ) + NEW metal1 ( 1396 777 ) via1_4 + NEW metal1 ( 1263 777 ) via1_4 ; + - storage_5_0.bit3.storage ( storage_5_0.bit3.obuf0 A ) ( storage_5_0.bit3.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1738 777 ) ( 1871 * ) + NEW metal1 ( 1871 777 ) via1_4 + NEW metal1 ( 1738 777 ) via1_4 ; + - storage_5_0.bit4.storage ( storage_5_0.bit4.obuf0 A ) ( storage_5_0.bit4.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 2232 777 ) ( 2365 * ) + NEW metal1 ( 2365 777 ) via1_4 + NEW metal2 ( 2365 777 ) via2_5 + NEW metal1 ( 2232 777 ) via1_4 + NEW metal2 ( 2232 777 ) via2_5 ; + - storage_5_0.bit5.storage ( storage_5_0.bit5.obuf0 A ) ( storage_5_0.bit5.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 2707 777 ) ( 2840 * ) + NEW metal1 ( 2840 777 ) via1_4 + NEW metal1 ( 2707 777 ) via1_4 ; + - storage_5_0.bit6.storage ( storage_5_0.bit6.obuf0 A ) ( storage_5_0.bit6.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 3201 777 ) ( 3334 * ) + NEW metal1 ( 3334 777 ) via1_4 + NEW metal1 ( 3201 777 ) via1_4 ; + - storage_5_0.gclock ( storage_5_0.cg GCK ) ( storage_5_0.bit6.bit CK ) ( storage_5_0.bit5.bit CK ) ( storage_5_0.bit4.bit CK ) ( storage_5_0.bit3.bit CK ) ( storage_5_0.bit2.bit CK ) ( storage_5_0.bit1.bit CK ) + ( storage_5_0.bit0.bit CK ) + USE SIGNAL + + ROUTED metal3 ( 180 777 ) ( 655 * ) + NEW metal2 ( 1149 777 ) ( * 791 ) + NEW metal3 ( 737 791 ) ( 1149 * ) + NEW metal3 ( 737 777 ) ( * 791 ) + NEW metal3 ( 655 777 ) ( 737 * ) + NEW metal2 ( 3087 777 ) ( * 791 ) + NEW metal2 ( 2593 777 ) ( * 791 ) + NEW metal3 ( 2593 791 ) ( 3087 * ) + NEW metal2 ( 2118 777 ) ( * 791 ) + NEW metal3 ( 2118 791 ) ( 2593 * ) + NEW metal2 ( 1624 777 ) ( * 791 ) + NEW metal3 ( 1624 791 ) ( 2118 * ) + NEW metal3 ( 1149 791 ) ( 1624 * ) + NEW metal3 ( 3087 791 ) ( 3638 * ) + NEW metal1 ( 655 777 ) via1_4 + NEW metal2 ( 655 777 ) via2_5 + NEW metal1 ( 180 777 ) via1_4 + NEW metal2 ( 180 777 ) via2_5 + NEW metal1 ( 1149 777 ) via1_4 + NEW metal2 ( 1149 791 ) via2_5 + NEW metal1 ( 3638 791 ) via1_4 + NEW metal2 ( 3638 791 ) via2_5 + NEW metal1 ( 3087 777 ) via1_4 + NEW metal2 ( 3087 791 ) via2_5 + NEW metal1 ( 2593 777 ) via1_4 + NEW metal2 ( 2593 791 ) via2_5 + NEW metal1 ( 2118 777 ) via1_4 + NEW metal2 ( 2118 791 ) via2_5 + NEW metal1 ( 1624 777 ) via1_4 + NEW metal2 ( 1624 791 ) via2_5 ; + - storage_5_0.select0_b ( storage_5_0.select_inv_0 ZN ) ( storage_5_0.bit6.obuf0 EN ) ( storage_5_0.bit5.obuf0 EN ) ( storage_5_0.bit4.obuf0 EN ) ( storage_5_0.bit3.obuf0 EN ) ( storage_5_0.bit2.obuf0 EN ) ( storage_5_0.bit1.obuf0 EN ) + ( storage_5_0.bit0.obuf0 EN ) + USE SIGNAL + + ROUTED metal3 ( 465 749 ) ( 940 * ) + NEW metal2 ( 3733 735 ) ( * 749 ) + NEW metal2 ( 3733 735 ) ( 3752 * ) + NEW metal3 ( 2878 749 ) ( 3372 * ) + NEW metal3 ( 2403 749 ) ( 2878 * ) + NEW metal3 ( 1909 749 ) ( 2403 * ) + NEW metal3 ( 1434 749 ) ( 1909 * ) + NEW metal3 ( 940 749 ) ( 1434 * ) + NEW metal3 ( 3372 749 ) ( 3733 * ) + NEW metal1 ( 940 749 ) via1_4 + NEW metal2 ( 940 749 ) via2_5 + NEW metal1 ( 465 749 ) via1_4 + NEW metal2 ( 465 749 ) via2_5 + NEW metal2 ( 3733 749 ) via2_5 + NEW metal1 ( 3752 735 ) via1_4 + NEW metal1 ( 3372 749 ) via1_4 + NEW metal2 ( 3372 749 ) via2_5 + NEW metal1 ( 2878 749 ) via1_4 + NEW metal2 ( 2878 749 ) via2_5 + NEW metal1 ( 2403 749 ) via1_4 + NEW metal2 ( 2403 749 ) via2_5 + NEW metal1 ( 1909 749 ) via1_4 + NEW metal2 ( 1909 749 ) via2_5 + NEW metal1 ( 1434 749 ) via1_4 + NEW metal2 ( 1434 749 ) via2_5 ; + - storage_5_0.we0 ( storage_5_0.gcand ZN ) ( storage_5_0.cg E ) + USE SIGNAL + + ROUTED metal3 ( 3505 777 ) ( 3714 * ) + NEW metal1 ( 3505 777 ) via1_4 + NEW metal2 ( 3505 777 ) via2_5 + NEW metal1 ( 3714 777 ) via1_4 + NEW metal2 ( 3714 777 ) via2_5 ; + - storage_6_0.bit0.storage ( storage_6_0.bit0.obuf0 A ) ( storage_6_0.bit0.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 294 903 ) ( 427 * ) + NEW metal1 ( 294 903 ) via1_4 + NEW metal1 ( 427 903 ) via1_4 ; + - storage_6_0.bit1.storage ( storage_6_0.bit1.obuf0 A ) ( storage_6_0.bit1.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 769 903 ) ( 902 * ) + NEW metal1 ( 769 903 ) via1_4 + NEW metal2 ( 769 903 ) via2_5 + NEW metal1 ( 902 903 ) via1_4 + NEW metal2 ( 902 903 ) via2_5 ; + - storage_6_0.bit2.storage ( storage_6_0.bit2.obuf0 A ) ( storage_6_0.bit2.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1263 903 ) ( 1396 * ) + NEW metal1 ( 1263 903 ) via1_4 + NEW metal1 ( 1396 903 ) via1_4 ; + - storage_6_0.bit3.storage ( storage_6_0.bit3.obuf0 A ) ( storage_6_0.bit3.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 1738 903 ) ( 1871 * ) + NEW metal1 ( 1738 903 ) via1_4 + NEW metal1 ( 1871 903 ) via1_4 ; + - storage_6_0.bit4.storage ( storage_6_0.bit4.obuf0 A ) ( storage_6_0.bit4.bit QN ) + USE SIGNAL + + ROUTED metal3 ( 2232 903 ) ( 2365 * ) + NEW metal1 ( 2232 903 ) via1_4 + NEW metal2 ( 2232 903 ) via2_5 + NEW metal1 ( 2365 903 ) via1_4 + NEW metal2 ( 2365 903 ) via2_5 ; + - storage_6_0.bit5.storage ( storage_6_0.bit5.obuf0 A ) ( storage_6_0.bit5.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 2707 903 ) ( 2840 * ) + NEW metal1 ( 2707 903 ) via1_4 + NEW metal1 ( 2840 903 ) via1_4 ; + - storage_6_0.bit6.storage ( storage_6_0.bit6.obuf0 A ) ( storage_6_0.bit6.bit QN ) + USE SIGNAL + + ROUTED metal2 ( 3201 903 ) ( 3334 * ) + NEW metal1 ( 3201 903 ) via1_4 + NEW metal1 ( 3334 903 ) via1_4 ; + - storage_6_0.gclock ( storage_6_0.cg GCK ) ( storage_6_0.bit6.bit CK ) ( storage_6_0.bit5.bit CK ) ( storage_6_0.bit4.bit CK ) ( storage_6_0.bit3.bit CK ) ( storage_6_0.bit2.bit CK ) ( storage_6_0.bit1.bit CK ) + ( storage_6_0.bit0.bit CK ) + USE SIGNAL + + ROUTED metal3 ( 180 903 ) ( 655 * ) + NEW metal2 ( 1149 889 ) ( * 903 ) + NEW metal3 ( 737 889 ) ( 1149 * ) + NEW metal3 ( 737 889 ) ( * 903 ) + NEW metal3 ( 655 903 ) ( 737 * ) + NEW metal2 ( 3087 889 ) ( * 903 ) + NEW metal2 ( 2593 889 ) ( * 903 ) + NEW metal3 ( 2593 889 ) ( 3087 * ) + NEW metal2 ( 2118 889 ) ( * 903 ) + NEW metal3 ( 2118 889 ) ( 2593 * ) + NEW metal2 ( 1624 889 ) ( * 903 ) + NEW metal3 ( 1624 889 ) ( 2118 * ) + NEW metal3 ( 1149 889 ) ( 1624 * ) + NEW metal3 ( 3087 889 ) ( 3638 * ) + NEW metal1 ( 655 903 ) via1_4 + NEW metal2 ( 655 903 ) via2_5 + NEW metal1 ( 180 903 ) via1_4 + NEW metal2 ( 180 903 ) via2_5 + NEW metal1 ( 1149 903 ) via1_4 + NEW metal2 ( 1149 889 ) via2_5 + NEW metal1 ( 3638 889 ) via1_4 + NEW metal2 ( 3638 889 ) via2_5 + NEW metal1 ( 3087 903 ) via1_4 + NEW metal2 ( 3087 889 ) via2_5 + NEW metal1 ( 2593 903 ) via1_4 + NEW metal2 ( 2593 889 ) via2_5 + NEW metal1 ( 2118 903 ) via1_4 + NEW metal2 ( 2118 889 ) via2_5 + NEW metal1 ( 1624 903 ) via1_4 + NEW metal2 ( 1624 889 ) via2_5 ; + - storage_6_0.select0_b ( storage_6_0.select_inv_0 ZN ) ( storage_6_0.bit6.obuf0 EN ) ( storage_6_0.bit5.obuf0 EN ) ( storage_6_0.bit4.obuf0 EN ) ( storage_6_0.bit3.obuf0 EN ) ( storage_6_0.bit2.obuf0 EN ) ( storage_6_0.bit1.obuf0 EN ) + ( storage_6_0.bit0.obuf0 EN ) + USE SIGNAL + + ROUTED metal3 ( 465 917 ) ( 940 * ) + NEW metal3 ( 3733 903 ) ( * 917 ) + NEW metal3 ( 3733 903 ) ( 3752 * ) + NEW metal3 ( 2878 917 ) ( 3372 * ) + NEW metal3 ( 2403 917 ) ( 2878 * ) + NEW metal3 ( 1909 917 ) ( 2403 * ) + NEW metal3 ( 1434 917 ) ( 1909 * ) + NEW metal3 ( 940 917 ) ( 1434 * ) + NEW metal3 ( 3372 917 ) ( 3733 * ) + NEW metal1 ( 940 917 ) via1_4 + NEW metal2 ( 940 917 ) via2_5 + NEW metal1 ( 465 917 ) via1_4 + NEW metal2 ( 465 917 ) via2_5 + NEW metal1 ( 3752 903 ) via1_4 + NEW metal2 ( 3752 903 ) via2_5 + NEW metal1 ( 3372 917 ) via1_4 + NEW metal2 ( 3372 917 ) via2_5 + NEW metal1 ( 2878 917 ) via1_4 + NEW metal2 ( 2878 917 ) via2_5 + NEW metal1 ( 2403 917 ) via1_4 + NEW metal2 ( 2403 917 ) via2_5 + NEW metal1 ( 1909 917 ) via1_4 + NEW metal2 ( 1909 917 ) via2_5 + NEW metal1 ( 1434 917 ) via1_4 + NEW metal2 ( 1434 917 ) via2_5 ; + - storage_6_0.we0 ( storage_6_0.gcand ZN ) ( storage_6_0.cg E ) + USE SIGNAL + + ROUTED metal3 ( 3505 903 ) ( 3714 * ) + NEW metal1 ( 3505 903 ) via1_4 + NEW metal2 ( 3505 903 ) via2_5 + NEW metal1 ( 3714 903 ) via1_4 + NEW metal2 ( 3714 903 ) via2_5 ; + - we[0] ( PIN we[0] ) ( storage_6_0.gcand A2 ) ( storage_5_0.gcand A2 ) ( storage_4_0.gcand A2 ) ( storage_3_0.gcand A2 ) ( storage_2_0.gcand A2 ) ( storage_1_0.gcand A2 ) + ( storage_0_0.gcand A2 ) + USE SIGNAL + + ROUTED metal2 ( 3676 175 ) ( * 217 ) + NEW metal3 ( 3676 175 ) ( 3948 * 0 ) + NEW metal2 ( 3676 63 ) ( * 175 ) + NEW metal2 ( 3676 217 ) ( * 343 ) + NEW metal2 ( 3676 343 ) ( * 497 ) + NEW metal2 ( 3676 497 ) ( * 623 ) + NEW metal2 ( 3676 623 ) ( * 777 ) + NEW metal2 ( 3676 777 ) ( * 903 ) + NEW metal1 ( 3676 217 ) via1_4 + NEW metal2 ( 3676 175 ) via2_5 + NEW metal1 ( 3676 63 ) via1_4 + NEW metal1 ( 3676 343 ) via1_4 + NEW metal1 ( 3676 497 ) via1_4 + NEW metal1 ( 3676 623 ) via1_4 + NEW metal1 ( 3676 777 ) via1_4 + NEW metal1 ( 3676 903 ) via1_4 ; +END NETS +END DESIGN diff --git a/src/ram/test/make_7x7_nangate45.lefok b/src/ram/test/make_7x7_nangate45.lefok new file mode 100644 index 00000000000..7fb088640e8 --- /dev/null +++ b/src/ram/test/make_7x7_nangate45.lefok @@ -0,0 +1,297 @@ +VERSION 5.8 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 2000 ; +END UNITS + +MACRO RAM7x7 + FOREIGN RAM7x7 0 0 ; + CLASS BLOCK ; + SIZE 39.52 BY 11.2 ; + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal3 ; + RECT 39.45 1.435 39.52 1.505 ; + END + END clk + PIN we[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal3 ; + RECT 39.45 1.715 39.52 1.785 ; + END + END we[0] + PIN addr[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal3 ; + RECT 39.45 2.275 39.52 2.345 ; + END + END addr[0] + PIN addr[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal3 ; + RECT 39.45 3.395 39.52 3.465 ; + END + END addr[1] + PIN addr[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal3 ; + RECT 39.45 1.155 39.52 1.225 ; + END + END addr[2] + PIN D[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 1.145 11.06 1.285 11.2 ; + END + END D[0] + PIN Q[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 3.385 11.06 3.525 11.2 ; + END + END Q[0] + PIN D[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 5.065 11.06 5.205 11.2 ; + END + END D[1] + PIN Q[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 8.425 11.06 8.565 11.2 ; + END + END Q[1] + PIN D[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 10.105 11.06 10.245 11.2 ; + END + END D[2] + PIN Q[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 12.905 11.06 13.045 11.2 ; + END + END Q[2] + PIN D[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 14.585 11.06 14.725 11.2 ; + END + END D[3] + PIN Q[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 17.385 11.06 17.525 11.2 ; + END + END Q[3] + PIN D[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 19.625 11.06 19.765 11.2 ; + END + END D[4] + PIN Q[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 22.985 11.06 23.125 11.2 ; + END + END Q[4] + PIN D[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 24.105 11.06 24.245 11.2 ; + END + END D[5] + PIN Q[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 27.465 11.06 27.605 11.2 ; + END + END Q[5] + PIN D[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 29.145 11.06 29.285 11.2 ; + END + END D[6] + PIN Q[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal4 ; + RECT 32.505 11.06 32.645 11.2 ; + END + END Q[6] + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER metal4 ; + RECT 35.93 11.06 36.07 11.2 ; + RECT 35.93 0 36.07 0.14 ; + RECT 26.93 11.06 27.07 11.2 ; + RECT 26.93 0 27.07 0.14 ; + RECT 17.93 11.06 18.07 11.2 ; + RECT 17.93 0 18.07 0.14 ; + RECT 8.93 11.06 9.07 11.2 ; + RECT 8.93 0 9.07 0.14 ; + LAYER metal1 ; + RECT 39.45 11.16 39.52 11.24 ; + RECT 0 11.16 0.07 11.24 ; + RECT 39.45 8.36 39.52 8.44 ; + RECT 0 8.36 0.07 8.44 ; + RECT 39.45 5.56 39.52 5.64 ; + RECT 0 5.56 0.07 5.64 ; + RECT 39.45 2.76 39.52 2.84 ; + RECT 0 2.76 0.07 2.84 ; + RECT 39.45 -0.04 39.52 0.04 ; + RECT 0 -0.04 0.07 0.04 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER metal4 ; + RECT 31.43 11.06 31.57 11.2 ; + RECT 31.43 0 31.57 0.14 ; + RECT 22.43 11.06 22.57 11.2 ; + RECT 22.43 0 22.57 0.14 ; + RECT 13.43 11.06 13.57 11.2 ; + RECT 13.43 0 13.57 0.14 ; + RECT 4.43 11.06 4.57 11.2 ; + RECT 4.43 0 4.57 0.14 ; + LAYER metal1 ; + RECT 39.45 9.76 39.52 9.84 ; + RECT 0 9.76 0.07 9.84 ; + RECT 39.45 6.96 39.52 7.04 ; + RECT 0 6.96 0.07 7.04 ; + RECT 39.45 4.16 39.52 4.24 ; + RECT 0 4.16 0.07 4.24 ; + RECT 39.45 1.36 39.52 1.44 ; + RECT 0 1.36 0.07 1.44 ; + END + END VDD + OBS + LAYER metal1 ; + RECT 0 -0.085 39.33 11.285 ; + RECT 39.33 -0.085 39.52 11.24 ; + LAYER metal2 ; + RECT 35.93 -0.07 36.07 0.315 ; + RECT 8.93 -0.07 9.07 0.42 ; + RECT 17.93 -0.07 18.07 0.42 ; + RECT 26.93 -0.07 27.07 0.42 ; + RECT 35.93 0.315 37.37 0.42 ; + RECT 8.93 0.42 11.53 0.56 ; + RECT 16.21 0.42 21.22 0.56 ; + RECT 25.9 0.42 30.91 0.56 ; + RECT 35.78 0.42 38.89 0.56 ; + RECT 1.01 0.56 39.27 2.1 ; + RECT 1.01 2.1 39.46 8.96 ; + RECT 1.01 8.96 39.27 9.1 ; + RECT 1.01 9.1 38.89 9.38 ; + RECT 1.01 9.38 36.07 9.52 ; + RECT 1.01 9.52 31.57 9.87 ; + RECT 1.01 9.87 1.08 9.94 ; + RECT 0.63 9.94 1.08 10.045 ; + RECT 5 9.87 10.77 10.045 ; + RECT 14.69 9.87 20.46 10.045 ; + RECT 24.38 9.87 30.15 10.045 ; + RECT 0.63 10.045 0.7 10.08 ; + RECT 5 10.045 10.39 10.08 ; + RECT 14.69 10.045 20.08 10.08 ; + RECT 24.38 10.045 29.77 10.08 ; + RECT 0.25 10.5 0.32 10.64 ; + RECT 5 10.08 5.07 10.64 ; + RECT 8.93 10.08 10.01 10.64 ; + RECT 14.69 10.08 19.7 10.64 ; + RECT 24.38 10.08 29.39 10.64 ; + RECT 8.93 10.64 9.07 11.27 ; + RECT 17.93 10.64 18.07 11.27 ; + RECT 26.93 10.64 27.07 11.27 ; + RECT 35.93 9.52 36.07 11.27 ; + LAYER metal3 ; + RECT 0.215 10.535 1.285 10.605 ; + RECT 1.735 0.595 4.43 9.485 ; + RECT 4.43 0.595 4.965 9.87 ; + RECT 4.965 0.595 5.205 10.605 ; + RECT 5.205 0.595 7.34 9.205 ; + RECT 7.34 0.455 8.195 9.205 ; + RECT 8.195 0.455 8.93 9.485 ; + RECT 8.93 -0.07 9.07 11.27 ; + RECT 9.07 0.455 10.245 10.605 ; + RECT 10.245 0.455 13.43 9.485 ; + RECT 13.43 0.455 14.585 9.87 ; + RECT 14.585 0.455 14.795 10.605 ; + RECT 14.795 0.455 17.93 9.485 ; + RECT 17.93 -0.07 18.07 11.27 ; + RECT 18.07 0.455 19.765 10.605 ; + RECT 19.765 0.455 24.105 9.87 ; + RECT 24.105 0.455 26.93 10.605 ; + RECT 26.93 -0.07 27.07 11.27 ; + RECT 27.07 0.455 29.425 10.605 ; + RECT 29.425 0.455 31.57 9.87 ; + RECT 31.57 0.455 32.655 9.485 ; + RECT 32.655 0.455 35.93 9.205 ; + RECT 35.93 -0.07 36.07 11.27 ; + RECT 36.07 0.455 37.37 9.205 ; + RECT 37.37 0.455 37.595 9.065 ; + RECT 37.595 0.455 38.925 8.925 ; + RECT 38.925 1.155 39.485 8.925 ; + RECT 39.485 2.135 39.495 2.205 ; + RECT 39.485 6.195 39.495 8.925 ; + LAYER metal4 ; + RECT 8.93 -0.07 9.07 0 ; + RECT 17.93 -0.07 18.07 0 ; + RECT 26.93 -0.07 27.07 0 ; + RECT 35.93 -0.07 36.07 0 ; + RECT 4.43 0 36.07 9.38 ; + RECT 3.385 9.38 36.07 10.5 ; + RECT 1.145 10.5 36.07 11.13 ; + RECT 4.43 11.13 36.07 11.2 ; + RECT 8.93 11.2 9.07 11.27 ; + RECT 17.93 11.2 18.07 11.27 ; + RECT 26.93 11.2 27.07 11.27 ; + RECT 35.93 11.2 36.07 11.27 ; + END +END RAM7x7 +END LIBRARY diff --git a/src/ram/test/make_7x7_nangate45.ok b/src/ram/test/make_7x7_nangate45.ok new file mode 100644 index 00000000000..46f3bad74d2 --- /dev/null +++ b/src/ram/test/make_7x7_nangate45.ok @@ -0,0 +1,112 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias +[WARNING ODB-0217] duplicate VIARULE (Via1Array-0) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via1Array-1) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via1Array-2) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via1Array-3) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via1Array-4) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via2Array-0) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via2Array-1) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via2Array-2) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via2Array-3) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via2Array-4) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via3Array-0) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via3Array-1) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via3Array-2) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via4Array-0) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via5Array-0) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via6Array-0) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via7Array-0) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via8Array-0) ignoring... +[WARNING ODB-0217] duplicate VIARULE (Via9Array-0) ignoring... +[INFO ODB-0394] Duplicate site FreePDK45_38x28_10R_NP_162NW_34O in Nangate45 already seen in Nangate45_tech +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 135 library cells +[INFO RAM-0003] Generating RAM7x7 +[INFO RAM-0016] Selected inverter cell INV_X1 +[INFO RAM-0016] Selected tristate cell TBUF_X1 +[INFO RAM-0016] Selected and2 cell AND2_X1 +[INFO RAM-0016] Selected clock gate cell CLKGATE_X1 +[INFO RAM-0016] Selected buffer cell BUF_X1 +[INFO RAM-0024] Behavioral Verilog written for RAM7x7 +[INFO PDN-0001] Inserting grid: ram_grid +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (4.5000 um, 4.0000 um) for VDD +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (9.0000 um, 8.0000 um) for VSS +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (13.5000 um, 4.0000 um) for VDD +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (18.0000 um, 8.0000 um) for VSS +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (22.5000 um, 4.0000 um) for VDD +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (27.0000 um, 8.0000 um) for VSS +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (31.5000 um, 4.0000 um) for VDD +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (36.0000 um, 8.0000 um) for VSS +[INFO PPL-0067] Restrict pins [ D[0] Q[0] D[1] Q[1] D[2] ... ] to region 0.00u-39.52u at the TOP edge. +[INFO PPL-0001] Number of available slots 184 +[INFO PPL-0002] Number of I/O 19 +[INFO PPL-0003] Number of I/O w/sink 19 +[INFO PPL-0004] Number of I/O w/o sink 0 +[INFO PPL-0005] Slots per section 200 +[INFO PPL-0008] Successfully assigned pins to sections. +[INFO PPL-0012] I/O nets HPWL: 120.70 um. +[INFO DPL-0001] Placed 35 filler instances. +[INFO DRT-0167] List of default vias: + Layer via2 + default via: via2_5 + Layer via3 + default via: via3_2 + Layer via4 + default via: via4_0 + Layer via5 + default via: via5_0 + Layer via6 + default via: via6_0 + Layer via7 + default via: via7_0 + Layer via8 + default via: via8_0 + Layer via9 + default via: via9_0 +[INFO DRT-0168] Init region query. +[INFO DRT-0033] active shape region query size = 0. +[INFO DRT-0033] FR_VIA shape region query size = 0. +[INFO DRT-0033] metal1 shape region query size = 4532. +[INFO DRT-0033] via1 shape region query size = 36. +[INFO DRT-0033] metal2 shape region query size = 72. +[INFO DRT-0033] via2 shape region query size = 36. +[INFO DRT-0033] metal3 shape region query size = 77. +[INFO DRT-0033] via3 shape region query size = 36. +[INFO DRT-0033] metal4 shape region query size = 74. +[INFO DRT-0033] via4 shape region query size = 0. +[INFO DRT-0033] metal5 shape region query size = 0. +[INFO DRT-0033] via5 shape region query size = 0. +[INFO DRT-0033] metal6 shape region query size = 0. +[INFO DRT-0033] via6 shape region query size = 0. +[INFO DRT-0033] metal7 shape region query size = 0. +[INFO DRT-0033] via7 shape region query size = 0. +[INFO DRT-0033] metal8 shape region query size = 0. +[INFO DRT-0033] via8 shape region query size = 0. +[INFO DRT-0033] metal9 shape region query size = 0. +[INFO DRT-0033] via9 shape region query size = 0. +[INFO DRT-0033] metal10 shape region query size = 0. +[INFO DRT-0178] Init guide query. +[INFO DRT-0036] active guide region query size = 0. +[INFO DRT-0036] FR_VIA guide region query size = 0. +[INFO DRT-0036] metal1 guide region query size = 264. +[INFO DRT-0036] via1 guide region query size = 0. +[INFO DRT-0036] metal2 guide region query size = 190. +[INFO DRT-0036] via2 guide region query size = 0. +[INFO DRT-0036] metal3 guide region query size = 132. +[INFO DRT-0036] via3 guide region query size = 0. +[INFO DRT-0036] metal4 guide region query size = 14. +[INFO DRT-0036] via4 guide region query size = 0. +[INFO DRT-0036] metal5 guide region query size = 0. +[INFO DRT-0036] via5 guide region query size = 0. +[INFO DRT-0036] metal6 guide region query size = 0. +[INFO DRT-0036] via6 guide region query size = 0. +[INFO DRT-0036] metal7 guide region query size = 0. +[INFO DRT-0036] via7 guide region query size = 0. +[INFO DRT-0036] metal8 guide region query size = 0. +[INFO DRT-0036] via8 guide region query size = 0. +[INFO DRT-0036] metal9 guide region query size = 0. +[INFO DRT-0036] via9 guide region query size = 0. +[INFO DRT-0036] metal10 guide region query size = 0. +[INFO DRT-0179] Init gr pin query. +No differences found. +No differences found. +No differences found. diff --git a/src/ram/test/make_7x7_nangate45.tcl b/src/ram/test/make_7x7_nangate45.tcl new file mode 100644 index 00000000000..49e6c450cca --- /dev/null +++ b/src/ram/test/make_7x7_nangate45.tcl @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2024-2025, The OpenROAD Authors +# +# Test: ram/make_7x7_nangate45 +# Verifies that generate_ram works correctly with the Nangate45 technology +# node using an intentionally odd 7-word x 1-byte (49-bit) configuration +# to exercise the decoder logic on a non-power-of-2 word count. + +source "helpers.tcl" + +set_thread_count [expr [cpu_count] / 4] + +read_liberty Nangate45/Nangate45_typ.lib + +read_lef Nangate45/Nangate45_tech.lef +read_lef Nangate45/Nangate45.lef + +set behavioral_file [make_result_file make_7x7_nangate45_behavioral.v] + +generate_ram \ + -mask_size 7 \ + -word_size 7 \ + -num_words 7 \ + -read_ports 1 \ + -storage_cell DFF_X1 \ + -power_pin VDD \ + -ground_pin VSS \ + -routing_layer {metal1 0.08} \ + -ver_layer {metal4 0.14 9} \ + -hor_layer {metal3 0.08 8} \ + -filler_cells {FILLCELL_X1 FILLCELL_X2 FILLCELL_X4 FILLCELL_X8} \ + -tapcell TAPCELL_X1 \ + -max_tap_dist 10 \ + -write_behavioral_verilog $behavioral_file + +set lef_file [make_result_file make_7x7_nangate45.lef] +write_abstract_lef $lef_file +diff_files make_7x7_nangate45.lefok $lef_file + +set def_file [make_result_file make_7x7_nangate45.def] +write_def $def_file +diff_files make_7x7_nangate45.defok $def_file + +diff_files make_7x7_nangate45_behavioral.vok $behavioral_file diff --git a/src/ram/test/make_7x7_nangate45_behavioral.vok b/src/ram/test/make_7x7_nangate45_behavioral.vok new file mode 100644 index 00000000000..430022499ee --- /dev/null +++ b/src/ram/test/make_7x7_nangate45_behavioral.vok @@ -0,0 +1,32 @@ +module RAM7x7 ( + clk, + D, + Q, + addr_rw, + we +); + input clk; + input [6:0] D; + output reg [6:0] Q; + input [2:0] addr_rw; + input [0:0] we; + + // memory array declaration + reg [6:0] mem[0:6]; + + // write logic + integer i; + always @(posedge clk) begin + for (i = 0; i < 1; i = i + 1) begin + if (we[i]) begin + mem[addr_rw][i*7 +:7] <= D[i*7 +:7]; + end + end + end + + // read logic + always @(*) begin + Q = mem[addr_rw]; + end + +endmodule diff --git a/src/ram/test/make_8x8.defok b/src/ram/test/make_8x8_sky130.defok similarity index 100% rename from src/ram/test/make_8x8.defok rename to src/ram/test/make_8x8_sky130.defok diff --git a/src/ram/test/make_8x8.lefok b/src/ram/test/make_8x8_sky130.lefok similarity index 100% rename from src/ram/test/make_8x8.lefok rename to src/ram/test/make_8x8_sky130.lefok diff --git a/src/ram/test/make_8x8.ok b/src/ram/test/make_8x8_sky130.ok similarity index 100% rename from src/ram/test/make_8x8.ok rename to src/ram/test/make_8x8_sky130.ok diff --git a/src/ram/test/make_8x8.tcl b/src/ram/test/make_8x8_sky130.tcl similarity index 76% rename from src/ram/test/make_8x8.tcl rename to src/ram/test/make_8x8_sky130.tcl index 73d78b0a724..b3ef72c312b 100644 --- a/src/ram/test/make_8x8.tcl +++ b/src/ram/test/make_8x8_sky130.tcl @@ -26,12 +26,12 @@ generate_ram \ -max_tap_dist 15 \ -write_behavioral_verilog $behavioral_file -set lef_file [make_result_file make_8x8.lef] +set lef_file [make_result_file make_8x8_sky130.lef] write_abstract_lef $lef_file -diff_files make_8x8.lefok $lef_file +diff_files make_8x8_sky130.lefok $lef_file -set def_file [make_result_file make_8x8.def] +set def_file [make_result_file make_8x8_sky130.def] write_def $def_file -diff_files make_8x8.defok $def_file +diff_files make_8x8_sky130.defok $def_file -diff_files make_8x8_behavioral.vok $behavioral_file +diff_files make_8x8_sky130_behavioral.vok $behavioral_file diff --git a/src/ram/test/make_8x8_behavioral.vok b/src/ram/test/make_8x8_sky130_behavioral.vok similarity index 100% rename from src/ram/test/make_8x8_behavioral.vok rename to src/ram/test/make_8x8_sky130_behavioral.vok diff --git a/src/ram/test/regression_tests.tcl b/src/ram/test/regression_tests.tcl index e37ce75db9f..3a5ac9bd078 100644 --- a/src/ram/test/regression_tests.tcl +++ b/src/ram/test/regression_tests.tcl @@ -1,3 +1,4 @@ record_tests { - make_8x8 + make_8x8_sky130 + make_7x7_nangate45 }