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TobskiTobski
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Various formatting fixes
1 parent c8483fc commit 0f913ee

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Lines changed: 16 additions & 16 deletions

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‎thsvs_simpler_vulkan_synchronization.h‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -263,7 +263,7 @@ typedef enum ThsvsAccessType {
263263
THSVS_ACCESS_COMPUTE_SHADER_WRITE, // Written as any resource in a compute shader
264264
THSVS_ACCESS_ANY_SHADER_WRITE, // Written as any resource in any shader
265265
THSVS_ACCESS_TRANSFER_WRITE, // Written as the destination of a transfer operation
266-
THSVS_ACCESS_HOST_PREINITIALIZED, // Data pre-filled by host before device access starts
266+
THSVS_ACCESS_HOST_PREINITIALIZED, // Data pre-filled by host before device access starts
267267
THSVS_ACCESS_HOST_WRITE, // Written on the host
268268

269269
// Requires VK_NV_ray_tracing to be enabled
@@ -572,7 +572,7 @@ const ThsvsVkAccessInfo ThsvsAccessMap[THSVS_NUM_ACCESS_TYPES] = {
572572
// THSVS_ACCESS_VERTEX_SHADER_READ_SAMPLED_IMAGE_OR_UNIFORM_TEXEL_BUFFER
573573
{ VK_PIPELINE_STAGE_VERTEX_SHADER_BIT,
574574
VK_ACCESS_SHADER_READ_BIT,
575-
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL },
575+
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL},
576576
// THSVS_ACCESS_VERTEX_SHADER_READ_OTHER
577577
{ VK_PIPELINE_STAGE_VERTEX_SHADER_BIT,
578578
VK_ACCESS_SHADER_READ_BIT,
@@ -585,7 +585,7 @@ const ThsvsVkAccessInfo ThsvsAccessMap[THSVS_NUM_ACCESS_TYPES] = {
585585
// THSVS_ACCESS_TESSELLATION_CONTROL_SHADER_READ_SAMPLED_IMAGE_OR_UNIFORM_TEXEL_BUFFER
586586
{ VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT,
587587
VK_ACCESS_SHADER_READ_BIT,
588-
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL },
588+
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL},
589589
// THSVS_ACCESS_TESSELLATION_CONTROL_SHADER_READ_OTHER
590590
{ VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT,
591591
VK_ACCESS_SHADER_READ_BIT,
@@ -598,7 +598,7 @@ const ThsvsVkAccessInfo ThsvsAccessMap[THSVS_NUM_ACCESS_TYPES] = {
598598
// THSVS_ACCESS_TESSELLATION_EVALUATION_SHADER_READ_SAMPLED_IMAGE_OR_UNIFORM_TEXEL_BUFFER
599599
{ VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT,
600600
VK_ACCESS_SHADER_READ_BIT,
601-
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL },
601+
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL},
602602
// THSVS_ACCESS_TESSELLATION_EVALUATION_SHADER_READ_OTHER
603603
{ VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT,
604604
VK_ACCESS_SHADER_READ_BIT,
@@ -611,7 +611,7 @@ const ThsvsVkAccessInfo ThsvsAccessMap[THSVS_NUM_ACCESS_TYPES] = {
611611
// THSVS_ACCESS_GEOMETRY_SHADER_READ_SAMPLED_IMAGE_OR_UNIFORM_TEXEL_BUFFER
612612
{ VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT,
613613
VK_ACCESS_SHADER_READ_BIT,
614-
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL },
614+
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL},
615615
// THSVS_ACCESS_GEOMETRY_SHADER_READ_OTHER
616616
{ VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT,
617617
VK_ACCESS_SHADER_READ_BIT,
@@ -663,7 +663,7 @@ const ThsvsVkAccessInfo ThsvsAccessMap[THSVS_NUM_ACCESS_TYPES] = {
663663
// THSVS_ACCESS_FRAGMENT_SHADER_READ_SAMPLED_IMAGE_OR_UNIFORM_TEXEL_BUFFER
664664
{ VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
665665
VK_ACCESS_SHADER_READ_BIT,
666-
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL },
666+
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL},
667667
// THSVS_ACCESS_FRAGMENT_SHADER_READ_COLOR_INPUT_ATTACHMENT
668668
{ VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
669669
VK_ACCESS_INPUT_ATTACHMENT_READ_BIT,
@@ -696,7 +696,7 @@ const ThsvsVkAccessInfo ThsvsAccessMap[THSVS_NUM_ACCESS_TYPES] = {
696696
// THSVS_ACCESS_COMPUTE_SHADER_READ_SAMPLED_IMAGE_OR_UNIFORM_TEXEL_BUFFER
697697
{ VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
698698
VK_ACCESS_SHADER_READ_BIT,
699-
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL },
699+
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL},
700700
// THSVS_ACCESS_COMPUTE_SHADER_READ_OTHER
701701
{ VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
702702
VK_ACCESS_SHADER_READ_BIT,
@@ -713,7 +713,7 @@ const ThsvsVkAccessInfo ThsvsAccessMap[THSVS_NUM_ACCESS_TYPES] = {
713713
// THSVS_ACCESS_ANY_SHADER_READ_SAMPLED_IMAGE
714714
{ VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
715715
VK_ACCESS_SHADER_READ_BIT,
716-
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL },
716+
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL},
717717
// THSVS_ACCESS_ANY_SHADER_READ_OTHER
718718
{ VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
719719
VK_ACCESS_SHADER_READ_BIT,
@@ -874,7 +874,7 @@ void thsvsGetVulkanMemoryBarrier(
874874
#endif
875875

876876
*pSrcStages |= pPrevAccessInfo->stageMask;
877-
877+
878878
// Add appropriate availability operations - for writes only.
879879
if (prevAccess > THSVS_END_OF_READ_ACCESS)
880880
pVkBarrier->srcAccessMask |= pPrevAccessInfo->accessMask;
@@ -895,14 +895,14 @@ void thsvsGetVulkanMemoryBarrier(
895895
assert(nextAccess < THSVS_END_OF_READ_ACCESS || thBarrier.nextAccessCount == 1);
896896
#endif
897897
*pDstStages |= pNextAccessInfo->stageMask;
898-
898+
899899
// Add visibility operations as necessary.
900900
// If the src access mask, this is a WAR hazard (or for some reason a "RAR"),
901901
// so the dst access mask can be safely zeroed as these don't need visibility.
902902
if (pVkBarrier->srcAccessMask != 0)
903903
pVkBarrier->dstAccessMask |= pNextAccessInfo->accessMask;
904904
}
905-
905+
906906
// Ensure that the stage masks are valid if no stages were determined
907907
if (*pSrcStages == 0)
908908
*pSrcStages = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
@@ -944,7 +944,7 @@ void thsvsGetVulkanBufferMemoryBarrier(
944944
#endif
945945

946946
*pSrcStages |= pPrevAccessInfo->stageMask;
947-
947+
948948
// Add appropriate availability operations - for writes only.
949949
if (prevAccess > THSVS_END_OF_READ_ACCESS)
950950
pVkBarrier->srcAccessMask |= pPrevAccessInfo->accessMask;
@@ -966,14 +966,14 @@ void thsvsGetVulkanBufferMemoryBarrier(
966966
#endif
967967

968968
*pDstStages |= pNextAccessInfo->stageMask;
969-
969+
970970
// Add visibility operations as necessary.
971971
// If the src access mask, this is a WAR hazard (or for some reason a "RAR"),
972972
// so the dst access mask can be safely zeroed as these don't need visibility.
973973
if (pVkBarrier->srcAccessMask != 0)
974974
pVkBarrier->dstAccessMask |= pNextAccessInfo->accessMask;
975975
}
976-
976+
977977
// Ensure that the stage masks are valid if no stages were determined
978978
if (*pSrcStages == 0)
979979
*pSrcStages = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
@@ -1016,7 +1016,7 @@ void thsvsGetVulkanImageMemoryBarrier(
10161016
#endif
10171017

10181018
*pSrcStages |= pPrevAccessInfo->stageMask;
1019-
1019+
10201020
// Add appropriate availability operations - for writes only.
10211021
if (prevAccess > THSVS_END_OF_READ_ACCESS)
10221022
pVkBarrier->srcAccessMask |= pPrevAccessInfo->accessMask;
@@ -1074,7 +1074,7 @@ void thsvsGetVulkanImageMemoryBarrier(
10741074
#endif
10751075

10761076
*pDstStages |= pNextAccessInfo->stageMask;
1077-
1077+
10781078
// Add visibility operations as necessary.
10791079
// If the src access mask, this is a WAR hazard (or for some reason a "RAR"),
10801080
// so the dst access mask can be safely zeroed as these don't need visibility.

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