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Alpha.5
Alpha.5 now correctly zeroes out the pipeline stage flags before trying to incrementally set bits on them... common theme here, whoops. (#5)
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Lines changed: 49 additions & 35 deletions

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‎README.md‎

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@@ -20,12 +20,16 @@ will be generated in that file.
2020

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## Version
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alpha.4
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alpha.5
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25-
Alpha.4 now correctly zeroes out the access types before trying to incrementally set bits on them (!)
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Alpha.5 now correctly zeroes out the pipeline stage flags before trying to incrementally set bits on them... common theme here, whoops.
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## Version History
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alpha.4
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Alpha.4 now correctly zeroes out the access types before trying to incrementally set bits on them (!)
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alpha.3
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Alpha.3 changes the following:

‎thsvs_simpler_vulkan_synchronization.h‎

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Original file line numberDiff line numberDiff line change
@@ -40,39 +40,43 @@ USAGE
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VERSION
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alpha.4
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alpha.5
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45-
Alpha.4 now correctly zeroes out the access types before trying to incrementally set bits on them (!)
45+
Alpha.5 now correctly zeroes out the pipeline stage flags before trying to incrementally set bits on them... common theme here, whoops.
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VERSION HISTORY
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alpha.4
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Alpha.4 now correctly zeroes out the access types before trying to incrementally set bits on them (!)
52+
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alpha.3
50-
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Alpha.3 changes the following:
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53-
Uniform and vertex buffer access in one enum, matching D3D12_RESOURCE_STATE_VERTEX_AND_CONSTANT_BUFFER:
54-
- THSVS_ACCESS_ANY_SHADER_READ_UNIFORM_BUFFER_OR_VERTEX_BUFFER
55-
56-
Color read *and* write access, matching D3D12_RESOURCE_STATE_RENDER_TARGET:
56+
57+
Uniform and vertex buffer access in one enum, matching D3D12_RESOURCE_STATE_VERTEX_AND_CONSTANT_BUFFER:
58+
- THSVS_ACCESS_ANY_SHADER_READ_UNIFORM_BUFFER_OR_VERTEX_BUFFER
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Color read *and* write access, matching D3D12_RESOURCE_STATE_RENDER_TARGET:
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- THSVS_ACCESS_COLOR_ATTACHMENT_READ_WRITE
58-
59-
Also the "THSVS_ACCESS_*_SHADER_READ_SAMPLED_IMAGE" enums have been renamed to the form "THSVS_ACCESS_*_SHADER_READ_SAMPLED_IMAGE_OR_UNIFORM_TEXEL_BUFFER"
60-
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Also the "THSVS_ACCESS_*_SHADER_READ_SAMPLED_IMAGE" enums have been renamed to the form "THSVS_ACCESS_*_SHADER_READ_SAMPLED_IMAGE_OR_UNIFORM_TEXEL_BUFFER"
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alpha.2
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Alpha.2 adds four new resource states for "ANY SHADER ACCESS":
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- THSVS_ACCESS_ANY_SHADER_READ_UNIFORM_BUFFER
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- THSVS_ACCESS_ANY_SHADER_READ_SAMPLED_IMAGE
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- THSVS_ACCESS_ANY_SHADER_READ_OTHER
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- THSVS_ACCESS_ANY_SHADER_WRITE
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alpha.1
70-
74+
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Alpha.1 adds three new resource states:
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- THSVS_ACCESS_GENERAL (Any access on the device)
7377
- THSVS_ACCESS_DEPTH_ATTACHMENT_WRITE_STENCIL_READ_ONLY (Write access to only the depth aspect of a depth/stencil attachment)
7478
- THSVS_ACCESS_STENCIL_ATTACHMENT_WRITE_DEPTH_READ_ONLY (Write access to only the stencil aspect of a depth/stencil attachment)
75-
79+
7680
It also fixes a couple of typos, and adds clarification as to when extensions need to be enabled to use a feature.
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alpha.0
@@ -162,9 +166,9 @@ typedef enum ThsvsAccessType {
162166
THSVS_ACCESS_NONE, // No access. Useful primarily for intialisation
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// Read access
165-
// Requires VK_NVX_device_generated_commands to be enabled
169+
// Requires VK_NVX_device_generated_commands to be enabled
166170
THSVS_ACCESS_COMMAND_BUFFER_READ_NVX, // Command buffer read operation as defined by NVX_device_generated_commands
167-
171+
168172
THSVS_ACCESS_INDIRECT_BUFFER, // Read as an indirect buffer for drawing or dispatch
169173
THSVS_ACCESS_INDEX_BUFFER, // Read as an index buffer for drawing
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THSVS_ACCESS_VERTEX_BUFFER, // Read as a vertex buffer for drawing
@@ -199,21 +203,21 @@ typedef enum ThsvsAccessType {
199203
THSVS_ACCESS_PRESENT, // Read by the presentation engine (i.e. vkQueuePresentKHR)
200204

201205
// Write access
202-
// Requires VK_NVX_device_generated_commands to be enabled
206+
// Requires VK_NVX_device_generated_commands to be enabled
203207
THSVS_ACCESS_COMMAND_BUFFER_WRITE_NVX, // Command buffer write operation
204-
208+
205209
THSVS_ACCESS_VERTEX_SHADER_WRITE, // Written as any resource in a vertex shader
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THSVS_ACCESS_TESSELLATION_CONTROL_SHADER_WRITE, // Written as any resource in a tessellation control shader
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THSVS_ACCESS_TESSELLATION_EVALUATION_SHADER_WRITE, // Written as any resource in a tessellation evaluation shader
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THSVS_ACCESS_GEOMETRY_SHADER_WRITE, // Written as any resource in a geometry shader
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THSVS_ACCESS_FRAGMENT_SHADER_WRITE, // Written as any resource in a fragment shader
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THSVS_ACCESS_COLOR_ATTACHMENT_WRITE, // Written as a color attachment during rendering, or via a subpass store op
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THSVS_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE, // Written as a depth/stencil attachment during rendering, or via a subpass store op
212-
213-
// Requires VK_KHR_maintenance2 to be enabled
216+
217+
// Requires VK_KHR_maintenance2 to be enabled
214218
THSVS_ACCESS_DEPTH_ATTACHMENT_WRITE_STENCIL_READ_ONLY, // Written as a depth aspect of a depth/stencil attachment during rendering, whilst the stencil aspect is read-only
215219
THSVS_ACCESS_STENCIL_ATTACHMENT_WRITE_DEPTH_READ_ONLY, // Written as a stencil aspect of a depth/stencil attachment during rendering, whilst the depth aspect is read-only
216-
220+
217221
THSVS_ACCESS_COMPUTE_SHADER_WRITE, // Written as any resource in a compute shader
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THSVS_ACCESS_ANY_SHADER_WRITE, // Written as any resource in any shader
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THSVS_ACCESS_TRANSFER_WRITE, // Written as the destination of a transfer operation
@@ -236,8 +240,8 @@ THSVS_IMAGE_LAYOUT_OPTIMAL is usually preferred.
236240
typedef enum ThsvsImageLayout {
237241
THSVS_IMAGE_LAYOUT_OPTIMAL, // Choose the most optimal layout for each usage. Performs layout transitions as appropriate for the access.
238242
THSVS_IMAGE_LAYOUT_GENERAL, // Layout accessible by all Vulkan access types on a device - no layout transitions except for presentation
239-
240-
// Requires VK_KHR_shared_presentable_image to be enabled. Can only be used for shared presentable images (i.e. single-buffered swapchains).
243+
244+
// Requires VK_KHR_shared_presentable_image to be enabled. Can only be used for shared presentable images (i.e. single-buffered swapchains).
241245
THSVS_IMAGE_LAYOUT_GENERAL_AND_PRESENTATION // As GENERAL, but also allows presentation engines to access it - no layout transitions
242246
} ThsvsImageLayout;
243247

@@ -598,7 +602,7 @@ const ThsvsVkAccessInfo ThsvsAccessMap[THSVS_NUM_ACCESS_TYPES] = {
598602
{ VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
599603
VK_ACCESS_UNIFORM_READ_BIT,
600604
VK_IMAGE_LAYOUT_UNDEFINED},
601-
// THSVS_ACCESS_ANY_SHADER_READ_UNIFORM_BUFFER_OR_VERTEX_BUFFER
605+
// THSVS_ACCESS_ANY_SHADER_READ_UNIFORM_BUFFER_OR_VERTEX_BUFFER
602606
{ VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
603607
VK_ACCESS_UNIFORM_READ_BIT | VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT,
604608
VK_IMAGE_LAYOUT_UNDEFINED},
@@ -671,7 +675,7 @@ const ThsvsVkAccessInfo ThsvsAccessMap[THSVS_NUM_ACCESS_TYPES] = {
671675
{ VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
672676
VK_ACCESS_SHADER_WRITE_BIT,
673677
VK_IMAGE_LAYOUT_GENERAL},
674-
678+
675679
// THSVS_ACCESS_ANY_SHADER_WRITE
676680
{ VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
677681
VK_ACCESS_SHADER_WRITE_BIT,
@@ -686,13 +690,13 @@ const ThsvsVkAccessInfo ThsvsAccessMap[THSVS_NUM_ACCESS_TYPES] = {
686690
VK_ACCESS_HOST_WRITE_BIT,
687691
VK_IMAGE_LAYOUT_GENERAL},
688692

689-
// THSVS_ACCESS_COLOR_ATTACHMENT_READ_WRITE
693+
// THSVS_ACCESS_COLOR_ATTACHMENT_READ_WRITE
690694
{ VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT,
691695
VK_ACCESS_COLOR_ATTACHMENT_READ_BIT | VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT,
692696
VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL},
693697
// THSVS_ACCESS_GENERAL
694698
{ VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
695-
VK_ACCESS_TYPE_MEMORY_READ_BIT | VK_ACCESS_TYPE_MEMORY_WRITE_BIT,
699+
VK_ACCESS_TYPE_MEMORY_READ_BIT | VK_ACCESS_TYPE_MEMORY_WRITE_BIT,
696700
VK_IMAGE_LAYOUT_GENERAL}
697701
};
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@@ -702,10 +706,12 @@ void thsvsGetVulkanMemoryBarrier(
702706
VkPipelineStageFlags* pDstStages,
703707
VkMemoryBarrier* pVkBarrier)
704708
{
709+
*pSrcStages = 0;
710+
*pDstStages = 0;
705711
pVkBarrier->sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER;
706712
pVkBarrier->pNext = NULL;
707-
pVkBarrier->srcAccessMask = 0;
708-
pVkBarrier->dstAccessMask = 0;
713+
pVkBarrier->srcAccessMask = 0;
714+
pVkBarrier->dstAccessMask = 0;
709715

710716
for (int i = 0; i < thBarrier.prevAccessCount; ++i)
711717
{
@@ -742,10 +748,12 @@ void thsvsGetVulkanBufferMemoryBarrier(
742748
VkPipelineStageFlags* pDstStages,
743749
VkBufferMemoryBarrier* pVkBarrier)
744750
{
751+
*pSrcStages = 0;
752+
*pDstStages = 0;
745753
pVkBarrier->sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER;
746754
pVkBarrier->pNext = NULL;
747-
pVkBarrier->srcAccessMask = 0;
748-
pVkBarrier->dstAccessMask = 0;
755+
pVkBarrier->srcAccessMask = 0;
756+
pVkBarrier->dstAccessMask = 0;
749757
pVkBarrier->srcQueueFamilyIndex = thBarrier.srcQueueFamilyIndex;
750758
pVkBarrier->dstQueueFamilyIndex = thBarrier.dstQueueFamilyIndex;
751759
pVkBarrier->buffer = thBarrier.buffer;
@@ -788,10 +796,12 @@ void thsvsGetVulkanImageMemoryBarrier(
788796
VkPipelineStageFlags* pDstStages,
789797
VkImageMemoryBarrier* pVkBarrier)
790798
{
799+
*pSrcStages = 0;
800+
*pDstStages = 0;
791801
pVkBarrier->sType = VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER;
792802
pVkBarrier->pNext = NULL;
793-
pVkBarrier->srcAccessMask = 0;
794-
pVkBarrier->dstAccessMask = 0;
803+
pVkBarrier->srcAccessMask = 0;
804+
pVkBarrier->dstAccessMask = 0;
795805
pVkBarrier->srcQueueFamilyIndex = thBarrier.srcQueueFamilyIndex;
796806
pVkBarrier->dstQueueFamilyIndex = thBarrier.dstQueueFamilyIndex;
797807
pVkBarrier->image = thBarrier.image;

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