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samueldrsamueldr
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arch: arm: Sync rk3399 DTs and bindings
This is required to directly import the dts from mainline. Signed-off-by: Samuel Dionne-Riel <samuel@dionne-riel.com>
1 parent 05aa651 commit 0780263

5 files changed

Lines changed: 123 additions & 28 deletions

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‎arch/arm/dts/rk3399-opp.dtsi‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
*/
55

66
/ {
7-
cluster0_opp: opp-table0 {
7+
cluster0_opp: opp-table-0 {
88
compatible = "operating-points-v2";
99
opp-shared;
1010

@@ -35,7 +35,7 @@
3535
};
3636
};
3737

38-
cluster1_opp: opp-table1 {
38+
cluster1_opp: opp-table-1 {
3939
compatible = "operating-points-v2";
4040
opp-shared;
4141

@@ -74,7 +74,7 @@
7474
};
7575
};
7676

77-
gpu_opp_table: opp-table2 {
77+
gpu_opp_table: opp-table-2 {
7878
compatible = "operating-points-v2";
7979

8080
opp00 {

‎arch/arm/dts/rk3399-u-boot.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@
4040
compatible = "rockchip,rk3399-dmc";
4141
devfreq-events = <&dfi>;
4242
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
43-
clocks = <&cru SCLK_DDRCLK>;
43+
clocks = <&cru SCLK_DDRC>;
4444
clock-names = "dmc_clk";
4545
reg = <0x0 0xffa80000 0x0 0x0800
4646
0x0 0xffa80800 0x0 0x1800

‎arch/arm/dts/rk3399.dtsi‎

Lines changed: 104 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,12 @@
124124
#cooling-cells = <2>; /* min followed by max */
125125
dynamic-power-coefficient = <436>;
126126
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
127+
128+
thermal-idle {
129+
#cooling-cells = <2>;
130+
duration-us = <10000>;
131+
exit-latency-us = <500>;
132+
};
127133
};
128134

129135
cpu_b1: cpu@101 {
@@ -136,6 +142,12 @@
136142
#cooling-cells = <2>; /* min followed by max */
137143
dynamic-power-coefficient = <436>;
138144
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
145+
146+
thermal-idle {
147+
#cooling-cells = <2>;
148+
duration-us = <10000>;
149+
exit-latency-us = <500>;
150+
};
139151
};
140152

141153
idle-states {
@@ -361,6 +373,54 @@
361373
status = "disabled";
362374
};
363375

376+
debug@fe430000 {
377+
compatible = "arm,coresight-cpu-debug", "arm,primecell";
378+
reg = <0 0xfe430000 0 0x1000>;
379+
clocks = <&cru PCLK_COREDBG_L>;
380+
clock-names = "apb_pclk";
381+
cpu = <&cpu_l0>;
382+
};
383+
384+
debug@fe432000 {
385+
compatible = "arm,coresight-cpu-debug", "arm,primecell";
386+
reg = <0 0xfe432000 0 0x1000>;
387+
clocks = <&cru PCLK_COREDBG_L>;
388+
clock-names = "apb_pclk";
389+
cpu = <&cpu_l1>;
390+
};
391+
392+
debug@fe434000 {
393+
compatible = "arm,coresight-cpu-debug", "arm,primecell";
394+
reg = <0 0xfe434000 0 0x1000>;
395+
clocks = <&cru PCLK_COREDBG_L>;
396+
clock-names = "apb_pclk";
397+
cpu = <&cpu_l2>;
398+
};
399+
400+
debug@fe436000 {
401+
compatible = "arm,coresight-cpu-debug", "arm,primecell";
402+
reg = <0 0xfe436000 0 0x1000>;
403+
clocks = <&cru PCLK_COREDBG_L>;
404+
clock-names = "apb_pclk";
405+
cpu = <&cpu_l3>;
406+
};
407+
408+
debug@fe610000 {
409+
compatible = "arm,coresight-cpu-debug", "arm,primecell";
410+
reg = <0 0xfe610000 0 0x1000>;
411+
clocks = <&cru PCLK_COREDBG_B>;
412+
clock-names = "apb_pclk";
413+
cpu = <&cpu_b0>;
414+
};
415+
416+
debug@fe710000 {
417+
compatible = "arm,coresight-cpu-debug", "arm,primecell";
418+
reg = <0 0xfe710000 0 0x1000>;
419+
clocks = <&cru PCLK_COREDBG_B>;
420+
clock-names = "apb_pclk";
421+
cpu = <&cpu_b1>;
422+
};
423+
364424
usbdrd3_0: usb@fe800000 {
365425
compatible = "rockchip,rk3399-dwc3";
366426
#address-cells = <2>;
@@ -1251,7 +1311,6 @@
12511311
compatible = "rockchip,iommu";
12521312
reg = <0x0 0xff650800 0x0 0x40>;
12531313
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1254-
interrupt-names = "vpu_mmu";
12551314
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
12561315
clock-names = "aclk", "iface";
12571316
#iommu-cells = <0>;
@@ -1273,7 +1332,6 @@
12731332
compatible = "rockchip,iommu";
12741333
reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
12751334
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1276-
interrupt-names = "vdec_mmu";
12771335
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
12781336
clock-names = "aclk", "iface";
12791337
power-domains = <&power RK3399_PD_VDU>;
@@ -1284,7 +1342,6 @@
12841342
compatible = "rockchip,iommu";
12851343
reg = <0x0 0xff670800 0x0 0x40>;
12861344
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1287-
interrupt-names = "iep_mmu";
12881345
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
12891346
clock-names = "aclk", "iface";
12901347
#iommu-cells = <0>;
@@ -1666,7 +1723,6 @@
16661723
compatible = "rockchip,iommu";
16671724
reg = <0x0 0xff8f3f00 0x0 0x100>;
16681725
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1669-
interrupt-names = "vopl_mmu";
16701726
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
16711727
clock-names = "aclk", "iface";
16721728
power-domains = <&power RK3399_PD_VOPL>;
@@ -1723,7 +1779,6 @@
17231779
compatible = "rockchip,iommu";
17241780
reg = <0x0 0xff903f00 0x0 0x100>;
17251781
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1726-
interrupt-names = "vopb_mmu";
17271782
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
17281783
clock-names = "aclk", "iface";
17291784
power-domains = <&power RK3399_PD_VOPB>;
@@ -1761,19 +1816,43 @@
17611816
compatible = "rockchip,iommu";
17621817
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
17631818
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1764-
interrupt-names = "isp0_mmu";
17651819
clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
17661820
clock-names = "aclk", "iface";
17671821
#iommu-cells = <0>;
17681822
power-domains = <&power RK3399_PD_ISP0>;
17691823
rockchip,disable-mmu-reset;
17701824
};
17711825

1826+
isp1: isp1@ff920000 {
1827+
compatible = "rockchip,rk3399-cif-isp";
1828+
reg = <0x0 0xff920000 0x0 0x4000>;
1829+
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1830+
clocks = <&cru SCLK_ISP1>,
1831+
<&cru ACLK_ISP1_WRAPPER>,
1832+
<&cru HCLK_ISP1_WRAPPER>;
1833+
clock-names = "isp", "aclk", "hclk";
1834+
iommus = <&isp1_mmu>;
1835+
phys = <&mipi_dsi1>;
1836+
phy-names = "dphy";
1837+
power-domains = <&power RK3399_PD_ISP1>;
1838+
status = "disabled";
1839+
1840+
ports {
1841+
#address-cells = <1>;
1842+
#size-cells = <0>;
1843+
1844+
port@0 {
1845+
reg = <0>;
1846+
#address-cells = <1>;
1847+
#size-cells = <0>;
1848+
};
1849+
};
1850+
};
1851+
17721852
isp1_mmu: iommu@ff924000 {
17731853
compatible = "rockchip,iommu";
17741854
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
17751855
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1776-
interrupt-names = "isp1_mmu";
17771856
clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
17781857
clock-names = "aclk", "iface";
17791858
#iommu-cells = <0>;
@@ -1878,6 +1957,7 @@
18781957
rockchip,grf = <&grf>;
18791958
#address-cells = <1>;
18801959
#size-cells = <0>;
1960+
#phy-cells = <0>;
18811961
status = "disabled";
18821962

18831963
ports {
@@ -1958,7 +2038,7 @@
19582038
#size-cells = <2>;
19592039
ranges;
19602040

1961-
gpio0: gpio0@ff720000 {
2041+
gpio0: gpio@ff720000 {
19622042
compatible = "rockchip,gpio-bank";
19632043
reg = <0x0 0xff720000 0x0 0x100>;
19642044
clocks = <&pmucru PCLK_GPIO0_PMU>;
@@ -1971,7 +2051,7 @@
19712051
#interrupt-cells = <0x2>;
19722052
};
19732053

1974-
gpio1: gpio1@ff730000 {
2054+
gpio1: gpio@ff730000 {
19752055
compatible = "rockchip,gpio-bank";
19762056
reg = <0x0 0xff730000 0x0 0x100>;
19772057
clocks = <&pmucru PCLK_GPIO1_PMU>;
@@ -1984,7 +2064,7 @@
19842064
#interrupt-cells = <0x2>;
19852065
};
19862066

1987-
gpio2: gpio2@ff780000 {
2067+
gpio2: gpio@ff780000 {
19882068
compatible = "rockchip,gpio-bank";
19892069
reg = <0x0 0xff780000 0x0 0x100>;
19902070
clocks = <&cru PCLK_GPIO2>;
@@ -1997,7 +2077,7 @@
19972077
#interrupt-cells = <0x2>;
19982078
};
19992079

2000-
gpio3: gpio3@ff788000 {
2080+
gpio3: gpio@ff788000 {
20012081
compatible = "rockchip,gpio-bank";
20022082
reg = <0x0 0xff788000 0x0 0x100>;
20032083
clocks = <&cru PCLK_GPIO3>;
@@ -2010,7 +2090,7 @@
20102090
#interrupt-cells = <0x2>;
20112091
};
20122092

2013-
gpio4: gpio4@ff790000 {
2093+
gpio4: gpio@ff790000 {
20142094
compatible = "rockchip,gpio-bank";
20152095
reg = <0x0 0xff790000 0x0 0x100>;
20162096
clocks = <&cru PCLK_GPIO4>;
@@ -2114,6 +2194,18 @@
21142194
};
21152195
};
21162196

2197+
cif {
2198+
cif_clkin: cif-clkin {
2199+
rockchip,pins =
2200+
<2 RK_PB2 3 &pcfg_pull_none>;
2201+
};
2202+
2203+
cif_clkouta: cif-clkouta {
2204+
rockchip,pins =
2205+
<2 RK_PB3 3 &pcfg_pull_none>;
2206+
};
2207+
};
2208+
21172209
edp {
21182210
edp_hpd: edp-hpd {
21192211
rockchip,pins =

‎drivers/clk/rockchip/clk_rk3399.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1049,7 +1049,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
10491049
* return 0 to satisfy clk_set_defaults during device probe.
10501050
*/
10511051
return 0;
1052-
case SCLK_DDRCLK:
1052+
case SCLK_DDRC:
10531053
ret = rk3399_ddr_set_clk(priv->cru, rate);
10541054
break;
10551055
case PCLK_EFUSE1024NS:

‎include/dt-bindings/clock/rk3399-cru.h‎

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
1-
/* SPDX-License-Identifier: GPL-2.0+ */
1+
/* SPDX-License-Identifier: GPL-2.0-or-later */
22
/*
33
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
4+
* Author: Xing Zheng <zhengxing@rock-chips.com>
45
*/
56

67
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
@@ -121,16 +122,18 @@
121122
#define SCLK_DPHY_RX0_CFG 165
122123
#define SCLK_RMII_SRC 166
123124
#define SCLK_PCIEPHY_REF100M 167
124-
#define SCLK_USBPHY0_480M_SRC 168
125-
#define SCLK_USBPHY1_480M_SRC 169
126-
#define SCLK_DDRCLK 170
127-
#define SCLK_TESTOUT2 171
125+
#define SCLK_DDRC 168
126+
#define SCLK_TESTCLKOUT1 169
127+
#define SCLK_TESTCLKOUT2 170
128+
#define SCLK_CIF_OUT_SRC 171
128129

129130
#define DCLK_VOP0 180
130131
#define DCLK_VOP1 181
131132
#define DCLK_VOP0_DIV 182
132133
#define DCLK_VOP1_DIV 183
133134
#define DCLK_M0_PERILP 184
135+
#define DCLK_VOP0_FRAC 185
136+
#define DCLK_VOP1_FRAC 186
134137

135138
#define FCLK_CM0S 190
136139

@@ -592,13 +595,13 @@
592595
#define SRST_P_SPI0 214
593596
#define SRST_P_SPI1 215
594597
#define SRST_P_SPI2 216
595-
#define SRST_P_SPI4 217
596-
#define SRST_P_SPI5 218
598+
#define SRST_P_SPI3 217
599+
#define SRST_P_SPI4 218
597600
#define SRST_SPI0 219
598601
#define SRST_SPI1 220
599602
#define SRST_SPI2 221
600-
#define SRST_SPI4 222
601-
#define SRST_SPI5 223
603+
#define SRST_SPI3 222
604+
#define SRST_SPI4 223
602605

603606
/* cru_softrst_con14 */
604607
#define SRST_I2S0_8CH 224
@@ -720,8 +723,8 @@
720723
#define SRST_H_CM0S_NOC 3
721724
#define SRST_DBG_CM0S 4
722725
#define SRST_PO_CM0S 5
723-
#define SRST_P_SPI3 6
724-
#define SRST_SPI3 7
726+
#define SRST_P_SPI6 6
727+
#define SRST_SPI6 7
725728
#define SRST_P_TIMER_0_1 8
726729
#define SRST_P_TIMER_0 9
727730
#define SRST_P_TIMER_1 10

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