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Add WaveActiveBitXor tests (llvm#971)
This PR adds tests for WaveActiveBitXor. WaveActiveBitXor only accepts uint and uint64 types. The PR also adds a control flow test, since this operation is convergent. Fixes llvm#896
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‎test/WaveOps/WaveActiveBitXor.convergence.test‎

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#--- source.hlsl
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StructuredBuffer<uint> In : register(t0);
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RWStructuredBuffer<uint> Out1 : register(u1); // branch A
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RWStructuredBuffer<uint> Out2 : register(u2); // branch B
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RWStructuredBuffer<uint> Out3 : register(u3); // reconverged
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RWStructuredBuffer<uint> Out4 : register(u4); // loop
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RWStructuredBuffer<uint> Out5 : register(u5); // divergent loop
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[numthreads(4,1,1)]
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void main(uint3 TID : SV_GroupThreadID) {
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uint V = In[TID.x];
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// divergent branch
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if (TID.x < 2)
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Out1[TID.x] = WaveActiveBitXor(V);
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else
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Out2[TID.x] = WaveActiveBitXor(V);
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// reconverged wave op
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Out3[TID.x] = WaveActiveBitXor(V);
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// loop case
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uint R = V;
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for (uint i = 0; i < 2; i++)
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R = WaveActiveBitXor(R);
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Out4[TID.x] = R;
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// divergent loop: each thread iterates TID.x times
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// thread 0: 0 iters, thread 1: 1 iter, thread 2: 2 iters, thread 3: 3 iters
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uint R2 = V;
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for (uint j = 0; j < TID.x; j++)
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R2 = WaveActiveBitXor(R2);
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Out5[TID.x] = R2;
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}
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#--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: In
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Format: UInt32
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Stride: 4
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Data: [ 0x11, 0x12, 0x14, 0x18 ]
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- Name: Out1
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Format: UInt32
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Stride: 4
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FillSize: 16
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- Name: Out2
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Format: UInt32
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Stride: 4
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FillSize: 16
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- Name: Out3
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Format: UInt32
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Stride: 4
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FillSize: 16
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- Name: Out4
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Format: UInt32
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Stride: 4
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FillSize: 16
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- Name: Out5
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Format: UInt32
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Stride: 4
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FillSize: 16
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- Name: ExpectedOut1
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Format: UInt32
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Stride: 4
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Data: [ 0x3, 0x3, 0x0, 0x0 ]
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- Name: ExpectedOut2
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Format: UInt32
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Stride: 4
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Data: [ 0x0, 0x0, 0xc, 0xc ]
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- Name: ExpectedOut3
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Format: UInt32
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Stride: 4
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Data: [ 0xf, 0xf, 0xf, 0xf ]
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- Name: ExpectedOut4
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Format: UInt32
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Stride: 4
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Data: [ 0x0, 0x0, 0x0, 0x0 ]
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- Name: ExpectedOut5
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Format: UInt32
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Stride: 4
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Data: [ 0x11, 0x1e, 0x0, 0x0 ]
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Results:
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- Result: ExpectedOut1
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Rule: BufferExact
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Actual: Out1
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Expected: ExpectedOut1
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- Result: ExpectedOut2
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Rule: BufferExact
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Actual: Out2
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Expected: ExpectedOut2
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- Result: ExpectedOut3
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Rule: BufferExact
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Actual: Out3
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Expected: ExpectedOut3
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- Result: ExpectedOut4
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Rule: BufferExact
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Actual: Out4
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Expected: ExpectedOut4
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- Result: ExpectedOut5
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Rule: BufferExact
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Actual: Out5
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Expected: ExpectedOut5
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DescriptorSets:
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- Resources:
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- Name: In
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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- Name: Out1
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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- Name: Out2
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 2
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Space: 0
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VulkanBinding:
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Binding: 2
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- Name: Out3
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 3
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Space: 0
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VulkanBinding:
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Binding: 3
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- Name: Out4
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 4
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Space: 0
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VulkanBinding:
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Binding: 4
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- Name: Out5
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 5
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Space: 0
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VulkanBinding:
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Binding: 5
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...
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#--- end
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# Bug: https://github.com/llvm/llvm-project/issues/188323
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# XFAIL: Vulkan && Clang
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# Bug: https://github.com/llvm/offload-test-suite/issues/1022
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# XFAIL: WARP
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o

‎test/WaveOps/WaveActiveBitXor.int.test‎

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#--- source.hlsl
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StructuredBuffer<uint4> In : register(t0);
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RWStructuredBuffer<uint> Out1 : register(u1);
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RWStructuredBuffer<uint2> Out2 : register(u2);
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RWStructuredBuffer<uint3> Out3 : register(u3);
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RWStructuredBuffer<uint4> Out4 : register(u4);
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RWStructuredBuffer<uint4> Out5 : register(u5);
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[numthreads(4,1,1)]
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void main(uint3 TID : SV_GroupThreadID) {
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uint4 V = In[TID.x];
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Out1[TID.x] = WaveActiveBitXor(V.x);
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// 3 thread case
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if (TID.x != 1)
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Out1[TID.x + 4] = WaveActiveBitXor(V.x);
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Out2[TID.x] = WaveActiveBitXor(V.xy);
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uint3 R3 = WaveActiveBitXor(V.xyz);
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Out3[TID.x].xyz = R3;
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Out4[TID.x] = WaveActiveBitXor(V);
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// constant folding
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Out5[TID.x] = WaveActiveBitXor(uint4(1,2,3,4));
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if (TID.x != 1)
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Out5[TID.x + 4] = WaveActiveBitXor(uint4(1,2,3,4));
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if (TID.x % 2)
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Out5[TID.x + 4 * 2] = WaveActiveBitXor(uint4(1,2,3,4));
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if (TID.x == 1)
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Out5[TID.x + 4 * 3] = WaveActiveBitXor(uint4(1,2,3,4));
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}
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#--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1,1,1]
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Buffers:
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- Name: In
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Format: UInt32
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Stride: 16
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Data: [
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0x11, 0x2, 0x4, 0x8,
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0x10, 0x20, 0x40, 0x80,
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0x100, 0x200, 0x400, 0x800,
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0x1000, 0x2000, 0x4000, 0x8000
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]
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- Name: Out1
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Format: UInt32
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Stride: 4
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FillSize: 32
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- Name: Out2
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Format: UInt32
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Stride: 8
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FillSize: 32
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- Name: Out3
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Format: UInt32
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Stride: 12
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FillSize: 48
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- Name: Out4
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Format: UInt32
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Stride: 16
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FillSize: 64
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- Name: Out5
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Format: UInt32
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Stride: 16
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FillSize: 256
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- Name: ExpectedOut1
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Format: UInt32
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Stride: 4
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Data: [ 0x1101, 0x1101, 0x1101, 0x1101, 0x1111, 0x0, 0x1111, 0x1111 ]
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- Name: ExpectedOut2
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Format: UInt32
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Stride: 8
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Data: [
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0x1101, 0x2222,
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0x1101, 0x2222,
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0x1101, 0x2222,
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0x1101, 0x2222
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]
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- Name: ExpectedOut3
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Format: UInt32
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Stride: 12
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Data: [
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0x1101, 0x2222, 0x4444,
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0x1101, 0x2222, 0x4444,
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0x1101, 0x2222, 0x4444,
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0x1101, 0x2222, 0x4444
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]
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- Name: ExpectedOut4
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Format: UInt32
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Stride: 16
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Data: [
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0x1101, 0x2222, 0x4444, 0x8888,
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0x1101, 0x2222, 0x4444, 0x8888,
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0x1101, 0x2222, 0x4444, 0x8888,
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0x1101, 0x2222, 0x4444, 0x8888
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]
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- Name: ExpectedOut5
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Format: UInt32
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Stride: 16
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Data: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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0x1, 0x2, 0x3, 0x4, 0x0, 0x0, 0x0, 0x0,
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0x1, 0x2, 0x3, 0x4, 0x1, 0x2, 0x3, 0x4,
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0, 0x1, 0x2, 0x3, 0x4,
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
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]
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Results:
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- Result: ExpectedOut1
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Rule: BufferExact
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Actual: Out1
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Expected: ExpectedOut1
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- Result: ExpectedOut2
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Rule: BufferExact
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Actual: Out2
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Expected: ExpectedOut2
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- Result: ExpectedOut3
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Rule: BufferExact
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Actual: Out3
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Expected: ExpectedOut3
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- Result: ExpectedOut4
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Rule: BufferExact
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Actual: Out4
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Expected: ExpectedOut4
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- Result: ExpectedOut5
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Rule: BufferExact
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Actual: Out5
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Expected: ExpectedOut5
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DescriptorSets:
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- Resources:
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- Name: In
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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- Name: Out1
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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- Name: Out2
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 2
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Space: 0
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VulkanBinding:
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Binding: 2
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- Name: Out3
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 3
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Space: 0
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VulkanBinding:
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Binding: 3
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- Name: Out4
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 4
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Space: 0
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VulkanBinding:
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Binding: 4
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- Name: Out5
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 5
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Space: 0
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VulkanBinding:
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Binding: 5
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...
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#--- end
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# Bug https://github.com/llvm/offload-test-suite/issues/1058
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# XFAIL: QC && DirectX
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# Bug https://github.com/llvm/offload-test-suite/issues/1058
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# XFAIL: QC && Clang && Vulkan
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_5 -fvk-use-dx-layout -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o

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