Enable ruff-specific checks and apply fixes. This removes many unnecessary str and list conversions.

Author: fdxmw

pyproject.toml

@@ -87,6 +87,8 @@ select = [
     "PLE", "PLW", "PLC",
     # refurb
     "FURB",
+    # ruff-specific checks
+    "RUF"
 ]
 ignore = [
     # Use ternary operator:
@@ -105,4 +107,8 @@ ignore = [
     # `import` should be at the top-level of a file:
     # PyRTL uses many function-level imports to avoid circular dependencies.
     "PLC0415",
+    # String/docstring/comment contains ambiguous <unicode>
+    "RUF001", "RUF002", "RUF003",
+    # `__all__` is not sorted
+    "RUF022",
 ]

pyrtl/analysis.py

@@ -228,7 +228,9 @@ def _memory_read_estimate(mem):
         tech_in_um = 0.130
         return 270 * tech_in_um**1.38 * bits**0.25 * ports**1.30 + 1.05
 
-    def max_freq(self, tech_in_nm: float = 130, ffoverhead: float = None) -> float:
+    def max_freq(
+        self, tech_in_nm: float = 130, ffoverhead: float | None = None
+    ) -> float:
         """Estimates the max frequency of a block in MHz.
 
         :param tech_in_nm: the size of the circuit technology to be estimated
@@ -338,7 +340,10 @@ def print_critical_paths(critical_paths):
 
 
 def yosys_area_delay(
-    library: str, abc_cmd: str = None, leave_in_dir: str = None, block: Block = None
+    library: str,
+    abc_cmd: str | None = None,
+    leave_in_dir: str | None = None,
+    block: Block = None,
 ) -> tuple[float, float]:
     """Synthesize with `Yosys <https://yosyshq.net/yosys/>`_ and return estimate of area
     and delay.
@@ -441,15 +446,15 @@ def path_sort_key(path):
                     for i, paths in enumerate(sorted(all_paths, key=path_sort_key)):
                         print(f"    Path {i}", file=file)
                         for path in paths:
-                            print(f"      {str(path)}", file=file)
+                            print(f"      {path}", file=file)
                 else:
                     print("    (No paths)", file=file)
 
 
 def paths(
     src: WireVector | Iterable[WireVector] = None,
     dst: WireVector | Iterable[WireVector] = None,
-    dst_nets: dict[WireVector, LogicNet] = None,
+    dst_nets: dict[WireVector, LogicNet] | None = None,
     block: Block = None,
 ) -> PathsResult:
     """Get the list of all paths from ``src`` to ``dst``.
@@ -530,9 +535,9 @@ def dfs(w, curr_path):
                 if dst_net not in curr_path:
                     if dst_net.op == "@":  # dests will be the read ports
                         for read_net in dst_net.op_param[1].readport_nets:
-                            dfs(read_net.dests[0], curr_path + [dst_net, read_net])
+                            dfs(read_net.dests[0], [*curr_path, dst_net, read_net])
                     else:
-                        dfs(dst_net.dests[0], curr_path + [dst_net])
+                        dfs(dst_net.dests[0], [*curr_path, dst_net])
 
         dfs(src, [])
         return paths

pyrtl/compilesim.py

@@ -105,8 +105,8 @@ class CompiledSimulation:
     def __init__(
         self,
         tracer: SimulationTrace = True,
-        register_value_map: dict[Register, int] = None,
-        memory_value_map: dict[MemBlock, dict[int, int]] = None,
+        register_value_map: dict[Register, int] | None = None,
+        memory_value_map: dict[MemBlock, dict[int, int]] | None = None,
         default_value: int = 0,
         block: Block = None,
     ):
@@ -161,7 +161,7 @@ def inspect(self, w: str) -> int:
         msg = "CompiledSimulation does not support inspecting internal WireVectors"
         raise PyrtlError(msg)
 
-    def step(self, provided_inputs: dict[str, int] = None, inputs=None):
+    def step(self, provided_inputs: dict[str, int] | None = None, inputs=None):
         if provided_inputs is None:
             provided_inputs = {}
         if inputs is not None:
@@ -175,9 +175,9 @@ def step(self, provided_inputs: dict[str, int] = None, inputs=None):
 
     def step_multiple(
         self,
-        provided_inputs: dict[str, list[int]] = None,
-        expected_outputs: dict[str, int] = None,
-        nsteps: int = None,
+        provided_inputs: dict[str, list[int]] | None = None,
+        expected_outputs: dict[str, int] | None = None,
+        nsteps: int | None = None,
         file=sys.stdout,
         stop_after_first_error: bool = False,
     ):

pyrtl/core.py

@@ -186,7 +186,7 @@ def __str__(self):
                     f"{name}[{addr}] & \\leftarrow @ \\, - & "
                     f"{data} we={we} ({extrainfo}) \\\\"
                 )
-            msg = f'error, unknown op "{str(self.op)}"'
+            msg = f'error, unknown op "{self.op}"'
             raise PyrtlInternalError(msg)
 
         # not in ipython
@@ -200,7 +200,7 @@ def __str__(self):
                 return f"{lhs} <-- m --  {memblock.name}[{rhs}]({extrainfo})"
             addr, data, we = (str(x) for x in self.args)
             return f"{memblock.name}[{addr}] <-- @ -- {data} we={we} ({extrainfo})"
-        msg = f'error, unknown op "{str(self.op)}"'
+        msg = f'error, unknown op "{self.op}"'
         raise PyrtlInternalError(msg)
 
     def __hash__(self):
@@ -461,7 +461,7 @@ def get_memblock_by_name(self, name: str, strict: bool = False) -> MemBlock:
         return None
 
     def wirevector_subset(
-        self, cls: tuple[type] = None, exclude: tuple[type] = ()
+        self, cls: tuple[type] | None = None, exclude: tuple[type] = ()
     ) -> set[WireVector]:
         """Return a subset of the ``Block's`` :class:`WireVectors<WireVector>`.
 
@@ -512,7 +512,7 @@ def wirevector_subset(
             return set(initial_set)
         return {x for x in initial_set if not isinstance(x, exclude)}
 
-    def logic_subset(self, op: tuple[str] = None) -> set[LogicNet]:
+    def logic_subset(self, op: tuple[str] | None = None) -> set[LogicNet]:
         """Return a subset of the ``Block's`` :class:`LogicNets<LogicNet>`.
 
         Filters :class:`LogicNets<LogicNet>` by their :attr:`~LogicNet.op`.
@@ -715,9 +715,8 @@ def sanity_check(self):
                 wirevector_names_list.remove(w)
             msg = (
                 "Duplicate wire names found for the following different signals: "
-                f"{repr(wirevector_names_list)} (make sure you are not using "
-                '"tmp" or "const_" as a signal name because those are reserved for '
-                "internal use)"
+                f'{wirevector_names_list} (make sure you are not using "tmp" or '
+                '"const_" as a signal name because those are reserved for internal use)'
             )
             raise PyrtlError(msg)
 
@@ -835,8 +834,7 @@ def sanity_check_memory_sync(self, wire_src_dict=None):
                     msg = (
                         f'memory "{net.op_param[1].name}" is not specified as '
                         f'asynchronous but has an index "{net.args[0].name}" that is '
-                        "not ready at the start of the cycle due to net "
-                        f'"{str(src_net)}"'
+                        f'not ready at the start of the cycle due to net "{src_net}"'
                     )
                     raise PyrtlError(msg)
 

pyrtl/corecircuits.py

@@ -750,7 +750,7 @@ def match_bitwidth(*args: WireVector, signed: bool = False) -> tuple[WireVector]
 
 def as_wires(
     val: WireVectorLike,
-    bitwidth: int = None,
+    bitwidth: int | None = None,
     truncating: bool = True,
     block: Block = None,
 ) -> WireVector:
@@ -817,7 +817,7 @@ def as_wires(
     if not isinstance(val, WireVector):
         msg = (
             "error, expecting a wirevector, int, or Verilog-style const string got "
-            f"{repr(val)} instead"
+            f"{val} instead"
         )
         raise PyrtlError(msg)
     if bitwidth == "0":
@@ -1020,7 +1020,7 @@ class Command(IntEnum):
     if len(keytypeset) != 1:
         msg = f"table mixes multiple types {keytypeset} as keys"
         raise PyrtlError(msg)
-    keytype = list(keytypeset)[0]
+    keytype = next(iter(keytypeset))
     # check that dictionary is complete for the enum
     try:
         enumkeys = list(keytype.__members__.values())

pyrtl/helperfuncs.py

@@ -40,7 +40,7 @@
 probeIndexer = _NameIndexer("Probe-")
 
 
-def probe(w: WireVector, name: str = None) -> WireVector:
+def probe(w: WireVector, name: str | None = None) -> WireVector:
     """Print useful information about a :class:`WireVector` in debug mode.
 
     ``probe`` can be inserted into a existing design easily because it returns the
@@ -272,7 +272,7 @@ def __exit__(self, *execinfo):
 
 
 def match_bitpattern(
-    w: WireVector, bitpattern: str, field_map: dict[str, str] = None
+    w: WireVector, bitpattern: str, field_map: dict[str, str] | None = None
 ) -> MatchedFields:
     """Returns a single-bit :class:`WireVector` that is ``1`` if and only if ``w``
     matches the ``bitpattern``, and a tuple containing the matched fields, if any.
@@ -587,7 +587,9 @@ def chop(w: WireVector, *segment_widths: int) -> list[WireVector]:
     return [w[s:e] for s, e in zip(starts, ends)]
 
 
-def input_list(names: str | list[str], bitwidth: int | list[int] = None) -> list[Input]:
+def input_list(
+    names: str | list[str], bitwidth: int | list[int] | None = None
+) -> list[Input]:
     """Allocate and return a list of :class:`Inputs<Input>`.
 
     See :func:`wirevector_list`. Equivalent to::
@@ -608,7 +610,7 @@ def input_list(names: str | list[str], bitwidth: int | list[int] = None) -> list
 
 
 def output_list(
-    names: str | list[str], bitwidth: int | list[int] = None
+    names: str | list[str], bitwidth: int | list[int] | None = None
 ) -> list[Output]:
     """Allocate and return a list of :class:`Outputs<Output>`.
 
@@ -630,7 +632,7 @@ def output_list(
 
 
 def register_list(
-    names: str | list[str], bitwidth: int | list[int] = None
+    names: str | list[str], bitwidth: int | list[int] | None = None
 ) -> list[Register]:
     """Allocate and return a list of :class:`Registers<Register>`.
 
@@ -653,7 +655,7 @@ def register_list(
 
 def wirevector_list(
     names: str | list[str],
-    bitwidth: int | list[int] = None,
+    bitwidth: int | list[int] | None = None,
     wvtype: type[WireVector] = WireVector,
 ) -> list[WireVector]:
     """Allocate and return a list of :class:`WireVectors<WireVector>`.
@@ -908,7 +910,7 @@ class ValueBitwidthTuple(NamedTuple):
 
 
 def infer_val_and_bitwidth(
-    rawinput: int | bool | str, bitwidth: int = None, signed: bool = False
+    rawinput: int | bool | str, bitwidth: int | None = None, signed: bool = False
 ) -> ValueBitwidthTuple:
     """Return a ``(value, bitwidth)`` :class:`tuple` inferred from the specified input.
 
@@ -967,7 +969,7 @@ def infer_val_and_bitwidth(
 
 
 def _convert_bool(
-    bool_val: bool, bitwidth: int = None, signed: bool = False
+    bool_val: bool, bitwidth: int | None = None, signed: bool = False
 ) -> ValueBitwidthTuple:
     if signed:
         msg = "error, booleans cannot be signed (convert to int first)"
@@ -982,7 +984,7 @@ def _convert_bool(
 
 
 def _convert_int(
-    val: numbers.Integral, bitwidth: int = None, signed: bool = False
+    val: numbers.Integral, bitwidth: int | None = None, signed: bool = False
 ) -> ValueBitwidthTuple:
     # Convert val from numbers.Integral to int. This avoids issues with
     # limited-precision types like numpy.int32.
@@ -1026,7 +1028,7 @@ def _convert_int(
 
 
 def _convert_verilog_str(
-    val: str, bitwidth: int = None, signed: bool = False
+    val: str, bitwidth: int | None = None, signed: bool = False
 ) -> ValueBitwidthTuple:
     if signed:
         msg = 'error, "signed" option with Verilog-style string constants not supported'
@@ -1981,7 +1983,7 @@ def __init__(
             block: Block = None,
             concatenated_type=WireVector,
             component_type=WireVector,
-            values: list = None,
+            values: list | None = None,
         ):
             # The concatenated WireVector contains all the _WireMatrix's wires.
             # WrappedWireVector (base class) will forward all attribute and
@@ -2144,7 +2146,7 @@ def one_hot_to_binary(w: WireVectorLike) -> WireVector:
 
 
 def binary_to_one_hot(
-    bit_position: WireVectorLike, max_bitwidth: int = None
+    bit_position: WireVectorLike, max_bitwidth: int | None = None
 ) -> WireVector:
     """Given a ``bit_position``, return a :class:`WireVector` with only that bit set to
     ``1``.

pyrtl/importexport.py

@@ -112,7 +112,7 @@ def input_from_blif(
     block: Block = None,
     merge_io_vectors: bool = True,
     clock_name: str = "clk",
-    top_model: str = None,
+    top_model: str | None = None,
 ):
     """Read an open BLIF file or string as input, updating the block appropriately.
 
@@ -528,10 +528,10 @@ def flop_next(data, enable, set, reset, prev):
                 "$_DFFSR_PPP": lambda: select(reset, 0, select(set, 1, data)),
                 "$_DFFSRE_PPPN_": lambda: select(
                     reset, 0, select(set, 1, select(~enable, data, prev))
-                ),  # noqa
+                ),
                 "$_DFFSRE_PPPP_": lambda: select(
                     reset, 0, select(set, 1, select(enable, data, prev))
-                ),  # noqa
+                ),
                 "$_SDFF_PN0_": lambda: select(~reset, 0, data),
                 "$_SDFF_PN1_": lambda: select(~reset, 1, data),
                 "$_SDFF_PP0_": lambda: select(reset, 0, data),
@@ -637,8 +637,8 @@ def instantiate(subckt):
 def input_from_verilog(
     verilog,
     clock_name: str = "clk",
-    toplevel: str = None,
-    leave_in_dir: bool = None,
+    toplevel: str | None = None,
+    leave_in_dir: bool | None = None,
     block: Block = None,
 ):
     """Read an open Verilog file or string as input via `Yosys
@@ -860,7 +860,7 @@ def name_list(wires):
     inputs, outputs, registers, wires, memories = _verilog_block_parts(block)
 
     # module name
-    io_list = ["clk"] + name_list(name_sorted(inputs)) + name_list(name_sorted(outputs))
+    io_list = ["clk", *name_list(name_sorted(inputs)), *name_list(name_sorted(outputs))]
     if add_reset:
         io_list.insert(1, "rst")
     if any(w.startswith("tmp") for w in io_list):
@@ -971,7 +971,7 @@ def name_sorted(wires):
             # someone please check if we need this special handling for scalars
             catlist = ", ".join(
                 [
-                    varname(net.args[0]) + f"[{str(i)}]"
+                    varname(net.args[0]) + f"[{i}]"
                     if len(net.args[0]) > 1
                     else varname(net.args[0])
                     for i in reversed(net.op_param)
@@ -1070,9 +1070,9 @@ def _to_verilog_footer(file):
 def output_verilog_testbench(
     dest_file,
     simulation_trace: SimulationTrace = None,
-    toplevel_include: str = None,
+    toplevel_include: str | None = None,
     vcd: str = "waveform.vcd",
-    cmd: str = None,
+    cmd: str | None = None,
     add_reset: bool | str = True,
     block: Block = None,
 ):
@@ -1217,7 +1217,7 @@ def default_value():
         print("    integer tb_iter;", file=dest_file)
 
     # Instantiate logic block
-    io_list = ["clk"] + name_list(name_sorted(inputs)) + name_list(name_sorted(outputs))
+    io_list = ["clk", *name_list(name_sorted(inputs)), *name_list(name_sorted(outputs))]
     if add_reset:
         io_list.insert(1, "rst")
     io_list_str = [f".{w:s}({w:s})" for w in io_list]
@@ -1286,7 +1286,9 @@ def default_value():
 #
 
 
-def output_to_firrtl(open_file, rom_blocks: list[RomBlock] = None, block: Block = None):
+def output_to_firrtl(
+    open_file, rom_blocks: list[RomBlock] | None = None, block: Block = None
+):
     """Output the block as FIRRTL code to the output file.
 
     If ROM is initialized in PyRTL code, you can pass in the :class:`RomBlocks` as a