Update CHANGELOG.md for 0.12 release

I'm planning to release 0.12 on Monday. 

Also add some contributor information to the changelog.

Author: fdxmw

CHANGELOG.md

@@ -6,25 +6,59 @@ releases published to PyPI are tracked here. No release candidates!
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.1.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## [0.12] - 2025-07-28
+
+### Added
+
+- [`GateGraph`](https://pyrtl.readthedocs.io/en/latest/blocks.html#module-pyrtl.gate_graph) is an alternative PyRTL logic representation, designed to simplify analysis.
+
+### Changed
+
+- Rewrote [`output_to_verilog`](https://pyrtl.readthedocs.io/en/latest/export.html#pyrtl.output_to_verilog) and [`output_verilog_testbench`](https://pyrtl.readthedocs.io/en/latest/export.html#pyrtl.output_verilog_testbench). The new implementation's output should be much easier to read:
+  - Single-use expressions are inlined.
+  - Try mangling unusable `WireVector` and `MemBlock` names first, before assigning them entirely new names.
+  - Add comments to the generated Verilog that show the un-mangled names.
+- Many documentation improvements:
+  - Most methods and functions now have examples.
+  - Consistently use canonical top-level `pyrtl.*` names, rather than module-level names (`pyrtl.WireVector`, not `pyrtl.wire.WireVector`).
+  - Enabled `intersphinx` for clickable standard library references (`list`, `dict`, etc).
+  - Set up `doctest` for examples, to verify that documentation examples still work.
+- Switched from `pylint` and `pycodestyle` to `ruff`:
+  - Applied many `ruff` fixes.
+  - Reformatted the code with `ruff format`.
+  - Updated `tox` to run `ruff check` and `ruff format`.
+
+### Removed
+
+- Removed remaining Python 2 support.
+
+### Fixed
+
+- Fixed XOR implementation in `and_inverter_synth` pass ([@EdwinChang24](https://github.com/EdwinChang24))
+- `output_verilog_testbench` should not re-initialize RomBlocks.
+- `FastSimulation` was not updating `init_menvalues` correctly. 
+- Specify bitwidths for Verilog initial register and memory values. They were previously unsized constants, which are implicitly 32-bit signed, which could cause surprises.
+
 ## [0.11.3] - 2025-06-12
 
 ### Added
 
-- An optimization pass to [optimize inverter chains](https://github.com/UCSBarchlab/PyRTL/blob/d5f8dbe53f54e61e1d54722449e4894b885243c7/pyrtl/passes.py#L130)
-- `one_hot_to_binary` encoder ([documentation](https://pyrtl.readthedocs.io/en/latest/helpers.html#pyrtl.one_hot_to_binary))
-- `binary_to_one_hot` decoder ([documentation](https://pyrtl.readthedocs.io/en/latest/helpers.html#pyrtl.binary_to_one_hot))
+- An optimization pass to [optimize inverter chains](https://github.com/UCSBarchlab/PyRTL/blob/d5f8dbe53f54e61e1d54722449e4894b885243c7/pyrtl/passes.py#L130) ([@gaborszita](https://github.com/gaborszita))
+- `one_hot_to_binary` encoder ([documentation](https://pyrtl.readthedocs.io/en/latest/helpers.html#pyrtl.one_hot_to_binary)) ([@vaaniarora](https://github.com/vaaniarora))
+- `binary_to_one_hot` decoder ([documentation](https://pyrtl.readthedocs.io/en/latest/helpers.html#pyrtl.binary_to_one_hot)) ([@vaaniarora](https://github.com/vaaniarora))
 
 ### Changed
 
 - More support for signed integers: Signed integers can now be used in `RomBlock`'s
-  `romdata`, `Simulation`'s `mem_value_map`, and Verilog-style register reset values.
+  `romdata`, `Simulation`'s `mem_value_map`
+  - And Verilog-style register reset values ([@PrajwalVandana](https://github.com/PrajwalVandana))
 - Improved documentation:
   - [conditional_assignment](https://pyrtl.readthedocs.io/en/latest/basic.html#module-pyrtl.conditional)
   - [WireVector equality](https://pyrtl.readthedocs.io/en/latest/basic.html#wirevector-equality)
 
 ### Fixed
 
-- Use iteration instead of recursion to avoid stack overflow in `find_producer`.
+- Use iteration instead of recursion to avoid stack overflow in `find_producer` ([@gaborszita](https://github.com/gaborszita))
 
 ## [0.11.2] - 2024-07-16
 
@@ -51,8 +85,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Changed
 
-- Major changes to `render_trace` visualization. See [examples and
-  documentation](https://pyrtl.readthedocs.io/en/latest/simtest.html#wave-renderer)
+- Major changes to `render_trace` visualization. See [examples and documentation](https://pyrtl.readthedocs.io/en/latest/simtest.html#wave-renderer)
 - Many documentation and release process improvements.
 
 ### Fixed