Enable ruff flake8-errmsg checks and apply fixes. This moves exception error messages to an err variable, to make tracebacks more readable:

Before (error message is partially repeated):
```
>>> pyrtl.Simulation()
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "/home/lauj/venv/pyrtlnet/lib/python3.12/site-packages/pyrtl/simulation.py", line 126, in __init__
    tracer = SimulationTrace()
             ^^^^^^^^^^^^^^^^^
  File "/home/lauj/venv/pyrtlnet/lib/python3.12/site-packages/pyrtl/simulation.py", line 1490, in __init__
    raise PyrtlError("There needs to be at least one named non-constant wire "
pyrtl.pyrtlexceptions.PyrtlError: There needs to be at least one named non-constant wire for simulation to be useful
```

After (only one copy of the error message):
```
>>> pyrtl.Simulation()
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "/home/lauj/projects/pyrtl/pyrtl/simulation.py", line 143, in __init__
    tracer = SimulationTrace()
             ^^^^^^^^^^^^^^^^^
  File "/home/lauj/projects/pyrtl/pyrtl/simulation.py", line 1582, in __init__
    raise PyrtlError(msg)
pyrtl.pyrtlexceptions.PyrtlError: There needs to be at least one named non-constant wire for simulation to be useful
```

Author: fdxmw

examples/example2-counter.py

@@ -52,7 +52,7 @@ def ripple_add(a, b, carry_in=0):
 # interesting features of PyRTL can be seen here:  WireVectors can be indexed
 # like lists, with [0] accessing the least significant bit and [1:] being an
 # example of the use of Python slicing syntax.  While you can add two lists
-# together in Python, a WireVector + Wirevector means "make an adder", so to
+# together in Python, a WireVector + WireVector means "make an adder", so to
 # concatenate the bits of two vectors one needs to use "concat".  Finally,
 # if we look at "carry_in" it seems to have a default value of the integer "0" but
 # is a WireVector at other times.  Python supports polymorphism throughout

examples/example5-introspection.py

@@ -26,10 +26,11 @@ def __getattr__(self, name):
         try:
             return self._pipeline_register_map[self._current_stage_num][name]
         except KeyError as exc:
-            raise pyrtl.PyrtlError(
+            msg = (
                 f'error, no pipeline register "{name}" defined for stage '
                 f"{self._current_stage_num}"
-            ) from exc
+            )
+            raise pyrtl.PyrtlError(msg) from exc
 
     def __setattr__(self, name, value):
         if name.startswith("_"):

ipynb-examples/example2-counter.ipynb

@@ -119,7 +119,7 @@
    "source": [
     "#### A couple interesting features of PyRTL can be seen here:\n",
     "* WireVectors can be indexed like lists, with [0] accessing the least significant bit and [1:] being an example of the use of Python slicing syntax.\n",
-    "* While you can add two lists together in python a WireVector + Wirevector means \"make an adder\" so to concatenate the bits of two vectors one need to use \"concat\".\n",
+    "* While you can add two lists together in python a WireVector + WireVector means \"make an adder\" so to concatenate the bits of two vectors one need to use \"concat\".\n",
     "* If we look at \"cin\" it seems to have a default value of the integer \"0\" but is a WireVector at other times.Python supports polymorphism throughout and PyRTL will cast integers and some other types to WireVectors when it can."
    ]
   },

pyproject.toml

@@ -69,6 +69,8 @@ select = [
     "B",
     # flake8-comprehensions
     "C4",
+    # flake8-errmsg
+    "EM",
     # flake8-future-annotations
     "FA",
     # flake8-return

pyrtl/analysis.py

@@ -85,10 +85,10 @@ def stdcell_estimate(net):
             return multiplier_stdcell_estimate(len(net.args[0]))
         if net.op in "m@":
             return 0  # memories handled elsewhere
-        raise PyrtlInternalError(
-            "Unable to estimate the following net "
-            f"due to unimplemented op :\n{str(net)}"
+        msg = (
+            "Unable to estimate the following net due to unimplemented op :\n{str(net)}"
         )
+        raise PyrtlInternalError(msg)
 
     block = working_block(block)
 
@@ -407,10 +407,12 @@ def extract_area_delay_from_yosys_output(yosys_output):
         print("---------------------------------------------", file=sys.stderr)
         print(str(exc.output).replace("\\n", "\n"), file=sys.stderr)
         print("---------------------------------------------", file=sys.stderr)
-        raise PyrtlError("Yosys call failed") from exc
+        msg = "Yosys call failed"
+        raise PyrtlError(msg) from exc
     except OSError as exc:
         print("Error with call to yosys...", file=sys.stderr)
-        raise PyrtlError("Call to yosys failed (not installed or on path?)") from exc
+        msg = "Call to yosys failed (not installed or on path?)"
+        raise PyrtlError(msg) from exc
     finally:
         if leave_in_dir is None:
             os.remove(temp_path)

pyrtl/compilesim.py

@@ -155,11 +155,11 @@ def inspect(self, w: str) -> int:
             pass
         else:
             if not vals:
-                raise PyrtlError("No context available. Please run a simulation step")
+                msg = "No context available. Please run a simulation step"
+                raise PyrtlError(msg)
             return vals[-1]
-        raise PyrtlError(
-            "CompiledSimulation does not support inspecting internal WireVectors"
-        )
+        msg = "CompiledSimulation does not support inspecting internal WireVectors"
+        raise PyrtlError(msg)
 
     def step(self, provided_inputs: dict[str, int] = None, inputs=None):
         if provided_inputs is None:
@@ -186,9 +186,8 @@ def step_multiple(
         if provided_inputs is None:
             provided_inputs = {}
         if not nsteps and len(provided_inputs) == 0:
-            raise PyrtlError(
-                "need to supply either input values or a number of steps to simulate"
-            )
+            msg = "need to supply either input values or a number of steps to simulate"
+            raise PyrtlError(msg)
 
         if len(provided_inputs) > 0:
             longest = sorted(
@@ -197,26 +196,30 @@ def step_multiple(
             msteps = len(longest[1])
             if nsteps:
                 if nsteps > msteps:
-                    raise PyrtlError(
-                        "nsteps is specified but is greater than the "
-                        "number of values supplied for each input"
+                    msg = (
+                        "nsteps is specified but is greater than the number of values "
+                        "supplied for each input"
                     )
+                    raise PyrtlError(msg)
             else:
                 nsteps = msteps
 
         if nsteps < 1:
-            raise PyrtlError("must simulate at least one step")
+            msg = "must simulate at least one step"
+            raise PyrtlError(msg)
 
         if list(filter(lambda value: len(value) < nsteps, provided_inputs.values())):
-            raise PyrtlError(
+            msg = (
                 "must supply a value for each provided wire for each step of simulation"
             )
+            raise PyrtlError(msg)
 
         if list(filter(lambda value: len(value) < nsteps, expected_outputs.values())):
-            raise PyrtlError(
-                "any expected outputs must have a supplied value "
-                "each step of simulation"
+            msg = (
+                "any expected outputs must have a supplied value each step of "
+                "simulation"
             )
+            raise PyrtlError(msg)
 
         failed = []
         for i in range(nsteps):
@@ -302,7 +305,8 @@ def run(self, inputs: list[dict[str, int]]):
                 start, count = self._inputpos[rname]
                 buf, sz = ibuf, self._ibufsz
             else:
-                raise PyrtlInternalError("Untraceable wire in tracer")
+                msg = "Untraceable wire in tracer"
+                raise PyrtlInternalError(msg)
             res = []
             for _step in range(steps):
                 val = 0
@@ -793,9 +797,11 @@ def _create_code(self, write):
         mems = {net.op_param[1] for net in self.block.logic_subset("m@")}
         for key in self._memmap:
             if key not in mems:
-                raise PyrtlError("unrecognized MemBlock in memory_value_map")
+                msg = "unrecognized MemBlock in memory_value_map"
+                raise PyrtlError(msg)
             if isinstance(key, RomBlock):
-                raise PyrtlError("RomBlock in memory_value_map")
+                msg = "RomBlock in memory_value_map"
+                raise PyrtlError(msg)
         self._declare_mem_helpers(write)
         roms = {mem for mem in mems if isinstance(mem, RomBlock)}
         self._declare_roms(write, roms)

pyrtl/conditional.py

@@ -92,9 +92,8 @@ def _push_condition(predicate):
     _check_under_condition()
     _depth += 1
     if predicate is not otherwise and len(predicate) > 1:
-        raise PyrtlError(
-            "all predicates for conditional assignments must be wirevectors of len 1"
-        )
+        msg = "all predicates for conditional assignments must be wirevectors of len 1"
+        raise PyrtlError(msg)
     _conditions_list_stack[-1].append(predicate)
     _conditions_list_stack.append([])
 
@@ -126,18 +125,21 @@ def _build_read_port(mem, addr):
 
 def _check_no_nesting():
     if _depth != 0:
-        raise PyrtlError("no nesting of conditional assignments allowed")
+        msg = "no nesting of conditional assignments allowed"
+        raise PyrtlError(msg)
 
 
 def _check_under_condition():
     if not currently_under_condition():
-        raise PyrtlError('conditional assignment "|=" only valid under a condition')
+        msg = 'conditional assignment "|=" only valid under a condition'
+        raise PyrtlError(msg)
 
 
 def _check_and_add_pred_set(lhs, pred_set):
     for test_set in _conflicts_map.setdefault(lhs, []):
         if _pred_sets_are_in_conflict(pred_set, test_set):
-            raise PyrtlError(f"conflicting conditions for {lhs}")
+            msg = f"conflicting conditions for {lhs}"
+            raise PyrtlError(msg)
     _conflicts_map[lhs].append(pred_set)
 
 
@@ -188,7 +190,8 @@ def _finalize(defaults):
                 else:
                     result = 0  # default for wire is "0"
             else:
-                raise PyrtlInternalError("unknown assignment in finalize")
+                msg = "unknown assignment in finalize"
+                raise PyrtlInternalError(msg)
             predlist = _predicate_map[lhs]
             for p, rhs in predlist:
                 result = select(p, truecase=rhs, falsecase=result)
@@ -237,9 +240,11 @@ def between_otherwise_and_current(predlist):
             pred_set.add((predicate, False))
 
     if select is None:
-        raise PyrtlError("problem with conditional assignment")
+        msg = "problem with conditional assignment"
+        raise PyrtlError(msg)
     if len(select) != 1:
-        raise PyrtlInternalError("conditional predicate with length greater than 1")
+        msg = "conditional predicate with length greater than 1"
+        raise PyrtlInternalError(msg)
 
     return select, pred_set