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Update output_to_verilog to inline temporary wires, using GateGraph: (#471)
* Update `output_to_verilog` to inline temporary wires, using `GateGraph`:
- Gates with user-specified names are never inlined.
- Unnamed constant Gates are always inlined, unless they are args to a bit-slice Gate.
- Unnamed non-constant Gates are inlined if:
- The Gate has one user, AND
- The Gate is not a MemBlock read, AND
- The Gate is not an arg to a bit-slice Gate.
This significantly reduces the amount of generated Verilog code.
Existing bugs fixed:
- `output_verilog_testbench` should not re-initialize RomBlocks.
- FastSimulation was not updating `init_menvalues` correctly.
- Specify bitwidths for Verilog initial register and memory values. They were
previously unsized constants, which are implicitly 32-bit signed, which could
cause surprises.
Add tests for these bugs.
Also:
- Improve Verilog identifier naming. Try replacing non-word characters with underscores before giving up and generating a new random name.
- When we mangle names, add a comment with the un-mangled name.
- Use sanitized MemBlock and RomBlock names instead of `mem_{memid}` names.
- Refactor `output_to_verilog` and `output_verilog_testbench` to share more code.
- Update `output_verilog_testbench` to use `GateGraph`.
- Define `GateGraph.__iter__` to make it easier to iterate over all Gates.
- Delete some disabled tests in `test_aes.py`.
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