Switch from relative imports to absolute imports. Absolute imports appears to be best practice, and relative imports seem to interfere with doctest.

Author: fdxmw

pyrtl/analysis.py

@@ -12,12 +12,12 @@
 import sys
 import collections
 
-from .core import working_block
-from .wire import Input, Output, Const, Register, WireVector
-from .pyrtlexceptions import PyrtlError, PyrtlInternalError
-from .importexport import output_to_verilog
-from .memory import RomBlock
-from .helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
+from pyrtl.core import working_block
+from pyrtl.wire import Input, Output, Const, Register, WireVector
+from pyrtl.pyrtlexceptions import PyrtlError, PyrtlInternalError
+from pyrtl.importexport import output_to_verilog
+from pyrtl.memory import RomBlock
+from pyrtl.helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
 
 
 # --------------------------------------------------------------------

pyrtl/compilesim.py

@@ -10,12 +10,12 @@
 import _ctypes
 from collections.abc import Mapping
 
-from .core import working_block, Block
-from .wire import Input, Output, Const, WireVector, Register
-from .memory import MemBlock, RomBlock
-from .pyrtlexceptions import PyrtlError, PyrtlInternalError
-from .simulation import SimulationTrace, _trace_sort_key
-from .helperfuncs import infer_val_and_bitwidth
+from pyrtl.core import working_block, Block
+from pyrtl.wire import Input, Output, Const, WireVector, Register
+from pyrtl.memory import MemBlock, RomBlock
+from pyrtl.pyrtlexceptions import PyrtlError, PyrtlInternalError
+from pyrtl.simulation import SimulationTrace, _trace_sort_key
+from pyrtl.helperfuncs import infer_val_and_bitwidth
 
 
 __all__ = ['CompiledSimulation']

pyrtl/conditional.py

@@ -162,8 +162,8 @@ def make_adder(x: pyrtl.WireVector) -> pyrtl.WireVector:
 # Use the objects "conditional_assignment" and "otherwise" as described above. The
 # classes below are internal implementation details.
 
-from .pyrtlexceptions import PyrtlError, PyrtlInternalError
-from .wire import WireVector, Const, Register
+from pyrtl.pyrtlexceptions import PyrtlError, PyrtlInternalError
+from pyrtl.wire import WireVector, Const, Register
 
 
 # -----------------------------------------------------------------------
@@ -320,7 +320,7 @@ def _pred_sets_are_in_conflict(pred_set_a, pred_set_b):
 
 def _finalize(defaults):
     """Build the required muxes and call back to WireVector to finalize the wirevector build."""
-    from .memory import MemBlock
+    from pyrtl.memory import MemBlock
     from pyrtl.corecircuits import select
     for lhs in _predicate_map:
         # handle memory write ports

pyrtl/core.py

@@ -10,26 +10,23 @@
 """
 from __future__ import annotations
 
-from typing import TYPE_CHECKING
-
-if TYPE_CHECKING:
-    from .wire import WireVector, Register
-    from .memory import MemBlock
-
 import collections
 import re
 import keyword
-from typing import NamedTuple
+from typing import NamedTuple, TYPE_CHECKING
 
-from .pyrtlexceptions import PyrtlError, PyrtlInternalError
+from pyrtl.pyrtlexceptions import PyrtlError, PyrtlInternalError
+
+if TYPE_CHECKING:
+    from pyrtl.wire import WireVector, Register
+    from pyrtl.memory import MemBlock
 
 
 # -----------------------------------------------------------------
 #    __        __   __
 #   |__) |    /  \ /  ` |__/
 #   |__) |___ \__/ \__, |  \
 #
-
 class LogicNet(NamedTuple):
     """The basic immutable datatype for storing a "net" in a netlist.
 
@@ -147,7 +144,7 @@ def __str__(self):
         lhs = ', '.join(str(x) for x in self.dests)
         options = '' if self.op_param is None else '(' + str(self.op_param) + ')'
 
-        from .helperfuncs import _currently_in_jupyter_notebook
+        from pyrtl.helperfuncs import _currently_in_jupyter_notebook
 
         if _currently_in_jupyter_notebook():
             # Output the working block as a Latex table
@@ -349,7 +346,7 @@ def __init__(self):
 
     def __str__(self):
         """String form has one LogicNet per line."""
-        from .helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
+        from pyrtl.helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
 
         if _currently_in_jupyter_notebook():
             _print_netlist_latex(list(self))
@@ -517,7 +514,7 @@ class _NetConnectionsDict(dict):
         nice error message when _MemIndexed is used as a lookup key.
         """
         def __missing__(self, key):
-            from .memory import _MemIndexed
+            from pyrtl.memory import _MemIndexed
 
             if isinstance(key, _MemIndexed):
                 raise PyrtlError(
@@ -572,7 +569,7 @@ def add_wire_dst(edge, node):
                 dst_list[edge] = [node]
 
         if include_virtual_nodes:
-            from .wire import Input, Output, Const
+            from pyrtl.wire import Input, Output, Const
             for wire in self.wirevector_subset((Input, Const)):
                 add_wire_src(wire, wire)
 
@@ -589,7 +586,7 @@ def add_wire_dst(edge, node):
 
     def _repr_svg_(self):
         """ IPython display support for Block. """
-        from .visualization import block_to_svg
+        from pyrtl.visualization import block_to_svg
         return block_to_svg(self)
 
     def __iter__(self):
@@ -602,7 +599,7 @@ def __iter__(self):
         Also, the order of the nets is not guaranteed to be the same
         over multiple iterations.
         """
-        from .wire import Input, Const, Register
+        from pyrtl.wire import Input, Const, Register
         src_dict, dest_dict = self.net_connections()
         to_clear = self.wirevector_subset((Input, Const, Register))
         cleared = set()
@@ -634,9 +631,8 @@ def sanity_check(self):
 
         :raise PyrtlError: If the ``Block`` is malformed.
         """
-
-        from .wire import Input, Const, Output
-        from .helperfuncs import get_stack, get_stacks
+        from pyrtl.wire import Input, Const, Output
+        from pyrtl.helperfuncs import get_stack, get_stacks
 
         # check for valid LogicNets (and wires)
         for net in self.logic:
@@ -734,7 +730,7 @@ def sanity_check_memory_sync(self, wire_src_dict=None):
         if wire_src_dict is None:
             wire_src_dict, wdd = self.net_connections()
 
-        from .wire import Input, Const
+        from pyrtl.wire import Input, Const
         sync_src = 'r'
         sync_prop = 'wcs'
         for net in sync_mems:
@@ -756,24 +752,24 @@ def sanity_check_memory_sync(self, wire_src_dict=None):
 
     def sanity_check_wirevector(self, w):
         """ Check that w is a valid WireVector type. """
-        from .wire import WireVector
+        from pyrtl.wire import WireVector
         if not isinstance(w, WireVector):
             raise PyrtlError(
                 'error attempting to pass an input of type "%s" '
                 'instead of WireVector' % type(w))
 
     def sanity_check_memblock(self, m):
         """ Check that m is a valid memblock type. """
-        from .memory import MemBlock
+        from pyrtl.memory import MemBlock
         if not isinstance(m, MemBlock):
             raise PyrtlError(
                 'error attempting to pass an input of type "%s" '
                 'instead of MemBlock' % type(m))
 
     def sanity_check_net(self, net):
         """ Check that net is a valid LogicNet. """
-        from .wire import Input, Output, Const, Register
-        from .memory import MemBlock
+        from pyrtl.wire import Input, Output, Const, Register
+        from pyrtl.memory import MemBlock
 
         # general sanity checks that apply to all operations
         if not isinstance(net, LogicNet):

pyrtl/corecircuits.py

@@ -4,12 +4,11 @@
 import math
 from typing import Union
 
-from .pyrtlexceptions import PyrtlError, PyrtlInternalError
-from .core import Block, LogicNet, working_block
-from .wire import Const, WireVector, WireVectorLike, WrappedWireVector
-from pyrtl.rtllib import barrel
-from pyrtl.rtllib import muxes
-from .conditional import otherwise
+from pyrtl.pyrtlexceptions import PyrtlError, PyrtlInternalError
+from pyrtl.core import Block, LogicNet, working_block
+from pyrtl.wire import Const, WireVector, WireVectorLike, WrappedWireVector
+from pyrtl.rtllib import barrel, muxes
+from pyrtl.conditional import otherwise
 
 
 def mux(index: WireVectorLike, *mux_ins: WireVector,
@@ -476,7 +475,7 @@ def myhardware(input_a, input_b):
         be dropped).
     :param block: ``Block`` to use for the returned ``WireVector``.
     """
-    from .memory import _MemIndexed
+    from pyrtl.memory import _MemIndexed
     block = working_block(block)
 
     if isinstance(val, (int, str)):
@@ -542,7 +541,7 @@ def bitfield_update(w: WireVectorLike, range_start: int, range_end: int, newvalu
 
     :return: ``w`` with some of the bits overwritten by ``newvalue``.
     """
-    from .corecircuits import concat_list
+    from pyrtl.corecircuits import concat_list
 
     w = as_wires(w)
     idxs = list(range(len(w)))  # we make a list of integers and slice those up to use as indexes

pyrtl/helperfuncs.py

@@ -10,18 +10,11 @@
 from functools import reduce
 from typing import Union, NamedTuple
 
-from .core import working_block, _NameIndexer, _get_debug_mode, Block
-from .pyrtlexceptions import PyrtlError, PyrtlInternalError
-from .wire import WireVector, Input, Output, Const, Register, WrappedWireVector
-from .corecircuits import (
-    as_wires,
-    rtl_all,
-    rtl_any,
-    concat,
-    concat_list,
-    select,
-    shift_left_logical
-)
+from pyrtl.core import working_block, _NameIndexer, _get_debug_mode, Block
+from pyrtl.pyrtlexceptions import PyrtlError, PyrtlInternalError
+from pyrtl.wire import WireVector, Input, Output, Const, Register, WrappedWireVector
+from pyrtl.corecircuits import (
+    as_wires, rtl_all, rtl_any, concat, concat_list, select, shift_left_logical)
 
 # -----------------------------------------------------------------
 #        ___       __   ___  __   __
@@ -187,12 +180,12 @@ class MatchedFields(NamedTuple):
     """``NamedTuple`` containing the matched fields, if any."""
 
     def __enter__(self):
-        from .conditional import _push_condition
+        from pyrtl.conditional import _push_condition
         _push_condition(self.matched)
         return self.fields
 
     def __exit__(self, *execinfo):
-        from .conditional import _pop_condition
+        from pyrtl.conditional import _pop_condition
         _pop_condition()
 
 

pyrtl/importexport.py

@@ -18,12 +18,12 @@
 import operator
 import typing
 
-from .pyrtlexceptions import PyrtlError, PyrtlInternalError
-from .core import working_block, _NameSanitizer, Block
-from .wire import WireVector, Input, Output, Const, Register, next_tempvar_name
-from .corecircuits import concat_list, rtl_all, rtl_any, select
-from .memory import RomBlock
-from .passes import two_way_concat, one_bit_selects
+from pyrtl.pyrtlexceptions import PyrtlError, PyrtlInternalError
+from pyrtl.core import working_block, _NameSanitizer, Block
+from pyrtl.wire import WireVector, Input, Output, Const, Register, next_tempvar_name
+from pyrtl.corecircuits import concat_list, rtl_all, rtl_any, select
+from pyrtl.memory import RomBlock
+from pyrtl.passes import two_way_concat, one_bit_selects
 
 
 def _natural_sort_key(key):

pyrtl/memory.py

@@ -14,11 +14,11 @@
 
 import collections
 
-from .pyrtlexceptions import PyrtlError
-from .core import working_block, LogicNet, _NameIndexer, Block
-from .wire import WireVector, Const, next_tempvar_name
-from .corecircuits import as_wires
-from .helperfuncs import infer_val_and_bitwidth
+from pyrtl.pyrtlexceptions import PyrtlError
+from pyrtl.core import working_block, LogicNet, _NameIndexer, Block
+from pyrtl.wire import WireVector, Const, next_tempvar_name
+from pyrtl.corecircuits import as_wires
+from pyrtl.helperfuncs import infer_val_and_bitwidth
 # ------------------------------------------------------------------------
 #
 #         ___        __   __          __        __   __
@@ -257,7 +257,7 @@ def _build_read_port(self, addr):
         return data
 
     def _assignment(self, item, val, is_conditional):
-        from .conditional import _build
+        from pyrtl.conditional import _build
 
         # Even though as_wires is already called on item already in the __getitem__ method,
         # we need to call it again here because __setitem__ passes the original item

pyrtl/passes.py

@@ -6,17 +6,18 @@
 
 import collections
 
-from .core import working_block, set_working_block, _get_debug_mode, LogicNet, PostSynthBlock
-from .helperfuncs import _NetCount
-from .corecircuits import (_basic_mult, _basic_add, _basic_sub, _basic_eq,
-                           _basic_lt, _basic_gt, _basic_select, concat_list,
-                           as_wires, concat)
-from .memory import MemBlock
-from .pyrtlexceptions import PyrtlError, PyrtlInternalError
-from .wire import WireVector, Input, Output, Const, Register
-from .transform import net_transform, _get_new_block_mem_instance, copy_block, replace_wires
-from . import transform
-from pyrtl import wire  # transform.all_nets looks better than all_nets
+from pyrtl.core import (
+    working_block, set_working_block, _get_debug_mode, LogicNet, PostSynthBlock)
+from pyrtl.helperfuncs import _NetCount
+from pyrtl.corecircuits import (
+    _basic_mult, _basic_add, _basic_sub, _basic_eq, _basic_lt, _basic_gt, _basic_select,
+    concat_list, as_wires, concat)
+from pyrtl.memory import MemBlock
+from pyrtl.pyrtlexceptions import PyrtlError, PyrtlInternalError
+from pyrtl.wire import WireVector, Input, Output, Const, Register
+from pyrtl.transform import (
+    net_transform, _get_new_block_mem_instance, copy_block, replace_wires)
+from pyrtl import transform  # transform.all_nets looks better than all_nets
 
 
 # --------------------------------------------------------------------
@@ -1017,7 +1018,7 @@ def two_way_fanout(block=None):
 
     :param block: block to update (defaults to working block)
     """
-    from .analysis import fanout
+    from pyrtl.analysis import fanout
     block = working_block(block)
 
     _, dst_map = block.net_connections()

pyrtl/rtllib/adders.py

@@ -1,7 +1,7 @@
 import itertools
 
 import pyrtl
-from . import libutils
+from pyrtl.rtllib import libutils
 
 
 def kogge_stone(a, b, cin=0):