Improve type annotations and documentation in core.py. Also:

* Upgrade `namedtuple`s to `NamedTuple`s for documented field names and types.
* Rearrange `blocks.rst` to feature `Block` first, as it's more likely to be
  useful to readers. Move `working_block` related functions to a new subsection.
* Simplify the `get_memblock_by_name` example.
* Remove more unneeded Sphinx directives.

Author: fdxmw

docs/analysis.rst

@@ -1,7 +1,5 @@
 .. PyRTL analysis master file
 
-.. default-domain:: pyrtl.rtllib
-
 =========================
 Analysis and Optimization
 =========================
@@ -27,6 +25,7 @@ Synthesis
 
 .. autoclass:: pyrtl.core.PostSynthBlock
    :show-inheritance:
+   :members:
 
 Individual Passes
 -----------------

docs/blocks.rst

@@ -1,16 +1,19 @@
-Logic Nets and Blocks
+Block and Logic Nets
 =====================
 
-LogicNets
----------
-
-.. autoclass:: pyrtl.core.LogicNet
-
-
 Blocks
 ------
 
 .. autoclass:: pyrtl.core.Block
+    :members:
+    :exclude-members: sanity_check_memblock, sanity_check_memory_sync, sanity_check_net, sanity_check_wirevector
+
+
+``working_block``
+^^^^^^^^^^^^^^^^^
+
+Most PyRTL operations operate on the global ``working_block`` by default. PyRTL
+provides several functions to inspect and manipulate the ``working_block``:
 
 .. autofunction:: pyrtl.core.working_block
 
@@ -20,20 +23,9 @@ Blocks
 
 .. autofunction:: pyrtl.core.temp_working_block
 
-.. autofunction:: pyrtl.core.Block.add_wirevector
-
-.. autofunction:: pyrtl.core.Block.remove_wirevector
-
-.. autofunction:: pyrtl.core.Block.add_net
-
-.. autofunction:: pyrtl.core.Block.get_memblock_by_name
-
-.. autofunction:: pyrtl.core.Block.wirevector_subset
-
-.. autofunction:: pyrtl.core.Block.logic_subset
-
-.. autofunction:: pyrtl.core.Block.get_wirevector_by_name
-
-.. autofunction:: pyrtl.core.Block.net_connections
+LogicNets
+---------
 
-.. autofunction:: pyrtl.core.Block.sanity_check
+.. autoclass:: pyrtl.core.LogicNet
+    :members:
+    :undoc-members:

docs/helpers.rst

@@ -42,6 +42,8 @@ Control Flow Hardware
 .. autofunction:: pyrtl.corecircuits.bitfield_update
 .. autofunction:: pyrtl.corecircuits.bitfield_update_set
 .. autoclass:: pyrtl.helperfuncs.MatchedFields
+    :members:
+    :undoc-members:
 .. autofunction:: pyrtl.helperfuncs.match_bitpattern
 
 Creating Lists of WireVectors

docs/rtllib.rst

@@ -1,7 +1,5 @@
 .. PyRTL rtllib master file
 
-.. default-domain:: pyrtl.rtllib
-
 ===========
 RTL Library
 ===========