@@ -410,10 +410,10 @@ def extract_area_delay_from_yosys_output(yosys_output):
410410def paths (src = None , dst = None , dst_nets = None , block = None ):
411411 """ Get the list of paths from src to dst.
412412
413- :param WireVector src: source wire(s) from which to trace your paths;
414- if None, will get paths from all Inputs
415- :param WireVector dst: destination wire(s) to which to trace your paths
416- if None, will get paths to all Outputs
413+ :param Union[ WireVector, Iterable[WireVector]] src: source wire(s) from which to
414+ trace your paths; if None, will get paths from all Inputs
415+ :param Union[ WireVector, Iterable[WireVector]] dst: destination wire(s) to which to
416+ trace your paths; if None, will get paths to all Outputs
417417 :param {WireVector: {LogicNet}} dst_nets: map from wire to set of nets where the
418418 wire is an argument; will compute it internally if not given via a
419419 call to pyrtl.net_connections()
@@ -448,10 +448,21 @@ def paths(src=None, dst=None, dst_nets=None, block=None):
448448 for output in block .wirevector_subset (cls = Output ):
449449 dst_nets .pop (output , None )
450450
451- src = block .wirevector_subset (cls = Input ) if src is None else {src }
452- dst = block .wirevector_subset (cls = Output ) if dst is None else {dst }
451+ if src is None :
452+ src = block .wirevector_subset (cls = Input )
453+ elif isinstance (src , WireVector ):
454+ src = {src }
455+ else :
456+ src = set (src )
457+
458+ if dst is None :
459+ dst = block .wirevector_subset (cls = Output )
460+ elif isinstance (dst , WireVector ):
461+ dst = {dst }
462+ else :
463+ dst = set (dst )
453464
454- def paths_src_dst (src , dst , block = None ):
465+ def paths_src_dst (src , dst ):
455466 paths = []
456467
457468 # Use DFS to get the paths [each a list of nets] from src wire to dst wire
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