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Update output_to_verilog to inline temporary wires, using GateGraph:
- Any Gate with a user-specified name is never inlined. - Unnamed constant Gates are always inlined. - Unnamed non-constant Gates are inlined if: - The Gate has one user, AND - The Gate is not a MemBlock read, AND - The Gate is not an arg to a bit-select Gate. This significantly reduces the amount of generated Verilog code. Also: - Update `output_verilog_testbench` to use `GateGraph`. - Define `GateGraph.__iter__` to make it easier to iterate over all Gates. - Delete some disabled tests in `test_aes.py`.
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docs/blocks.rst

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@@ -52,5 +52,5 @@ GateGraphs
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.. autoclass:: pyrtl.GateGraph
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:members:
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:special-members: __init__, __str__
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:special-members: __init__, __iter__, __str__
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pyrtl/gate_graph.py

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@@ -712,6 +712,9 @@ class GateGraph:
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gates: set[Gate]
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"""A :class:`set` of all :class:`Gates<Gate>` in the ``GateGraph``.
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Similar to :attr:`~GateGraph.__iter__`, except that ``gates`` is a :class:`set`
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rather than an :class:`~collections.abc.Iterable`.
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.. doctest only::
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>>> import pyrtl
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self.gates, key=lambda gate: gate.name if gate.name else "~~~"
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)
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return "\n".join([str(gate) for gate in sorted_gates])
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def __iter__(self):
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"""Iterate over each gate in the :class:`GateGraph`.
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Similar to :attr:`~GateGraph.gates`, except that ``__iter__`` returns an
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:class:`~collections.abc.Iterable` rather than a :class:`set`.
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.. doctest only::
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>>> import pyrtl
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>>> pyrtl.reset_working_block()
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Example::
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>>> a = pyrtl.Input(name="a", bitwidth=2)
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>>> b = pyrtl.Input(name="b", bitwidth=2)
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>>> sum = a + b
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>>> sum.name = "sum"
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>>> gate_graph = pyrtl.GateGraph()
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>>> sorted(gate.name for gate in gate_graph)
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['a', 'b', 'sum']
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"""
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return iter(self.gates)

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