Commit c94b341
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Update
- Any Gate with a user-specified name is never inlined.
- Unnamed constant Gates are always inlined.
- Unnamed non-constant Gates are inlined if:
- The Gate has one user, AND
- The Gate is not a MemBlock read, AND
- The Gate is not an arg to a bit-select Gate.
This significantly reduces the amount of generated Verilog code.
Also:
- Update `output_verilog_testbench` to use `GateGraph`.
- Define `GateGraph.__iter__` to make it easier to iterate over all Gates.
- Delete some disabled tests in `test_aes.py`.output_to_verilog to inline temporary wires, using GateGraph:1 parent 3deeedd commit c94b341
6 files changed
Lines changed: 682 additions & 857 deletions
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- rtllib
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