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pyVHDLModelTreesitter #106

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@domWalters

Hi,

Not an issue, more of a signpost to something people might find useful.

Last year I spent some of my free time developing a library that creates a pyVHDLModel from inspection of a tree-sitter parse of a VHDL source file as an alternative to pyVHDLParser or similar.

I haven't worked on it for a while, but something I'm doing at work has prompted me to freshen it up a bit and actually package it to pypi.

The source is available here: https://gitlab.com/dawalters/pyVHDLModelTreesitter

It is nowhere close to complete, but you can at the very least:

  • Parse a document containing Entity declarations.
    • Other design units are not supported atm.
      • NotImplementedError will be raised if anything unsupported is found.
  • Obtain the LibraryClauses, UseClauses, GenericConstantInterfaceItems, and PortSignalInterfaceItems related to an Entity.
    • GenericConstantInterfaceItem and PortSignalInterfaceItem support SimpleSubtypeSymbols only.

Some examples I run tests against can be seen here.

I'm gonna be adding some more features in the short term, primarily so I can read arbitrary files from an existing library and pull generics and ports for use in some documentation / git error checking hooks.


Note: There is a reasonably high chance I have misunderstood, or misinterpreted parts of pyVHDLModel. So the output may not be exactly correct.

Happy to make changes where this has happened.

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