Analyze indpended files or unused packages

[el3ctrician]

Design.Analyze() raises VHDLModelException: Compile order is not yet computed from dependency graph. when the design contains VHDL files with no cross-dependencies.
i wrote a parser for .f file that adds it to my analyzer and i had a package file which was not used.
The guard at __init__.py:1902 requires EdgeCount >= VertexCount - 1 (N-1 edges for N vertices), but ComputeCompileOrder() only creates edges between files that have a dependency relationship. Independent files are valid in VHDL and should compile in any order.
i think the check should be changed to:

if self._compileOrderGraph.VertexCount == 0:
 raise VHDLModelException(...)

Since file must exists but no dependency between them exists. Maybe i am missing something but i never had any issues with non used packages/entities added to my project in any tool matter of fact it's a questionable design pattern i have seen where you always include a set of package in the compile list regardless if you are going to use them or not.
How to reproduce?

from pathlib import Path
import tempfile, os
from pyGHDL.dom.NonStandard import Design, Document
# Two independent entities, no cross-dependencies
tmp = Path(tempfile.mkdtemp())
(tmp / "a.vhd").write_text("entity a is end entity;")
(tmp / "b.vhd").write_text("entity b is end entity;")
d = Design()
d.AllowBlackbox = True
lib = d.GetLibrary("lib")
for f in [tmp / "a.vhd", tmp / "b.vhd"]:
 d.AddDocument(Document(f), lib)
os.environ["GHDL_PREFIX"] = "/path/to/ghdl/lib"
d.LoadDefaultLibraries()
d.Analyze() # raises VHDLModelException

let me know what do you think about it ? i am willing to push a fix quickly for that