fix: import on the top of the file/module

Author: umarcor

vunit/builtins.py

@@ -11,6 +11,7 @@
 
 from os.path import join, abspath, dirname, basename
 from glob import glob
+from vunit.test.common import simulator_check
 
 VHDL_PATH = abspath(join(dirname(__file__), "vhdl"))
 VERILOG_PATH = abspath(join(dirname(__file__), "verilog"))
@@ -80,8 +81,6 @@ def _add_data_types(self, use_external=None, impls=None):
 
 #        Add sources corresponding to VHPIDIRECT arrays (or their placeholders)
 
-        from vunit.test.common import simulator_check
-
         use_ext = [False]
         files = [None]