extend(examples/vhdl/array_axis_vcs): integration of foreign C declarations with GHDL

umarcor · umarcor · commit 752415e4b4b2 · 2019-06-05T01:54:43.000+02:00
diff --git a/examples/vhdl/array_axis_vcs/run.py b/examples/vhdl/array_axis_vcs/run.py
@@ -4,6 +4,7 @@
 #
 # Copyright (c) 2014-2019, Lars Asplund lars.anders.asplund@gmail.com
 
+import os
 from os.path import join, dirname
 from vunit import VUnit
 
@@ -21,4 +22,10 @@
 
 # vu.set_sim_option('modelsim.init_files.after_load',['runall_addwave.do'])
 
+c_obj = join(root, 'src', 'test', 'main.o')
+
+print(os.popen('gcc -fPIC -rdynamic -c '+join(root, 'src/**/*.c')+' -o '+c_obj).read())
+
+vu.set_objects([c_obj])
+
 vu.main()
diff --git a/examples/vhdl/array_axis_vcs/src/test/main.c b/examples/vhdl/array_axis_vcs/src/test/main.c
@@ -0,0 +1,84 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+extern int ghdl_main (int argc, char **argv);
+
+int32_t *V[2];
+uint32_t length = 100;
+
+// get_param is used by GHDL to retrieve parameter values (integers).
+uint32_t get_param(uint32_t w) {
+  uint32_t o = 0;
+  switch(w) {
+    case 0 : // buffer length
+      o = length;
+      break;;
+    case 1 : // data width (in bits)
+      o = 8*sizeof(int32_t);
+      break;;
+    case 2 : // fifo depth
+      o = 5;
+      break;;
+  }
+  printf("get_p(%d): %d\n", w, (int)o);
+  return o;
+}
+
+// get_addr is used by GHDL to retrieve pointers to the base addresses of the buffers.
+uintptr_t get_addr(uint32_t w) {
+  //printf("get_addr(%d): %p\n", w, (void *)V[w]o);
+  return (uintptr_t)V[w];
+}
+
+// check evaluates if the result produced by the UUT is equivalent to some other softwre procedure.
+int check(int32_t *I, int32_t *O, uint32_t l) {
+  int i;
+  for ( i=0 ; i<l ; i++ ) {
+    if ( I[i] != O[i] ) {
+      printf("check failed! %d: %d %d\n", i, I[i], O[i]);
+      return -1;
+    }
+  }
+  printf("check successful\n");
+  return 0;
+}
+
+// main is the entrypoint to the application.
+int main(int argc, char **argv) {
+
+  // Optionally, some of the CLI arguments can be processed by the software app and others forwarded to GHDL.
+  int gargc = argc;
+  char **gargv = argv;
+
+  // Allocate the memory buffers that are to be shared between the software and the simulation.
+  int i;
+  for (i=0 ; i<2 ; i++) {
+    V[i] = (int32_t *) malloc(length*sizeof(uint32_t));
+    if ( V[i] == NULL ) {
+      perror("execution of malloc() failed!\n");
+      return -1;
+    }
+  }
+
+  // Initialize one of the buffers with random data.
+  for (i=0 ; i<length ; i++) {
+    V[0][i]=i*100+rand()/(RAND_MAX/100);
+  }
+
+  // Execute the simulation to let the UUT copy the data from one buffer to another.
+  ghdl_main(gargc, gargv);
+
+  // Check that the UUT did what it was expected to do.
+  printf("> Call 'check'\n");
+  if ( check(V[0], V[1], length) != 0 ) {
+    printf("check failed!\n");
+    return -1;
+  }
+
+  // Free the allocated memory, since we don't need it anymore.
+  free(V[0]);
+  free(V[1]);
+
+  return 0;
+}
diff --git a/examples/vhdl/array_axis_vcs/src/test/pkg_c.vhd b/examples/vhdl/array_axis_vcs/src/test/pkg_c.vhd
@@ -0,0 +1,51 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2019, Lars Asplund lars.anders.asplund@gmail.com
+
+package pkg_c is
+
+  function get_param(f: integer) return integer;
+    attribute foreign of get_param :
+      function is "VHPIDIRECT get_param";
+
+  constant stream_length : integer := get_param(0);
+
+  type buffer_t is array(integer range 0 to stream_length-1) of integer;
+  type buffer_p is access buffer_t;
+
+  impure function get_addr(f: integer) return buffer_p;
+    attribute foreign of get_addr :
+      function is "VHPIDIRECT get_addr";
+
+  type buffet_t_prot is protected
+    procedure init ( i: integer );
+    procedure set ( i: integer; v: integer);
+    impure function get (i: integer) return integer;
+  end protected buffet_t_prot;
+
+end pkg_c;
+
+package body pkg_c is
+  function get_param(f: integer) return integer is begin
+    assert false report "VHPI" severity failure;
+  end get_param;
+
+  impure function get_addr(f: integer) return buffer_p is begin
+    assert false report "VHPI" severity failure;
+  end get_addr;
+
+  type buffet_t_prot is protected body
+    variable var: buffer_p;
+    procedure init ( i: integer ) is begin
+      var := get_addr(i);
+    end procedure;
+    procedure set ( i: integer; v: integer ) is begin
+      var(i) := v;
+    end procedure;
+    impure function get ( i: integer ) return integer is begin
+      return var(i);
+    end get;
+  end protected body buffet_t_prot;
+end pkg_c;
diff --git a/examples/vhdl/array_axis_vcs/src/test/tb_c_axis_loop.vhd b/examples/vhdl/array_axis_vcs/src/test/tb_c_axis_loop.vhd
@@ -0,0 +1,131 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2019, Lars Asplund lars.anders.asplund@gmail.com
+
+-- This testbench is a Minimum Working Example (MWE) of VUnit's resources to read/write data from a buffer
+-- allocated in a foreign C application, and to verify AXI4-Stream components. Data is sent to an AXI4-Stream
+-- Slave. The AXI4-Stream Slave is expected to be connected to an AXI4-Stream Master either directly or
+-- (preferredly) through a FIFO, thus composing a loopback. Therefore, as data is pushed to the AXI4-Stream
+-- Slave interface, the output is read from the AXI4-Stream Master interface and it is saved back to the buffer
+-- shared with the software application.
+
+library ieee;
+context ieee.ieee_std_context;
+
+library vunit_lib;
+context vunit_lib.vunit_context;
+context vunit_lib.vc_context;
+
+use work.pkg_c.all;
+
+entity tb_c_axis_loop is
+  generic (
+    runner_cfg : string;
+    tb_path    : string
+  );
+end entity;
+
+architecture tb of tb_c_axis_loop is
+  -- Simulation constants
+
+  constant clk_period : time    := 20 ns;
+  constant data_width : natural := get_param(1);
+  constant fifo_depth : natural := get_param(2);
+
+  -- AXI4Stream Verification Components
+
+  constant m_axis : axi_stream_master_t := new_axi_stream_master(data_length => data_width);
+  constant s_axis : axi_stream_slave_t := new_axi_stream_slave(data_length => data_width);
+
+  -- tb signals and variables
+
+  signal clk, rst, rstn     : std_logic := '0';
+  signal start, sent, saved : boolean   := false;
+  shared variable ibuffer, obuffer: buffet_t_prot;
+
+begin
+
+  clk <= not clk after (clk_period/2);
+  rstn <= not rst;
+
+  main: process
+    procedure run_test is begin
+      info("Init test");
+      wait until rising_edge(clk); start <= true;
+      wait until rising_edge(clk); start <= false;
+      wait until (sent and saved and rising_edge(clk));
+      info("Test done");
+    end procedure;
+  begin
+    test_runner_setup(runner, runner_cfg);
+    while test_suite loop
+      if run("test") then
+        ibuffer.init(0);
+        obuffer.init(1);
+        rst <= '1';
+        wait for 15*clk_period;
+        rst <= '0';
+        run_test;
+        end if;
+    end loop;
+    test_runner_cleanup(runner);
+    wait;
+  end process;
+
+--
+
+  stimuli: process
+    variable last : std_logic;
+  begin
+    sent <= false;
+    wait until start and rising_edge(clk);
+
+    for y in 0 to stream_length-1 loop
+      wait until rising_edge(clk);
+      push_axi_stream(net, m_axis, std_logic_vector(to_signed(ibuffer.get(y), data_width)) , tlast => '0');
+    end loop;
+
+    info("m_I sent!");
+
+    wait until rising_edge(clk);
+    sent <= true;
+    wait;
+  end process;
+
+  save: process
+    variable o : std_logic_vector(31 downto 0);
+    variable last : std_logic:='0';
+  begin
+    saved <= false;
+    wait until start and rising_edge(clk);
+    wait for 50*clk_period;
+
+    for y in 0 to stream_length-1 loop
+      pop_axi_stream(net, s_axis, tdata => o, tlast => last);
+      obuffer.set(y,to_integer(signed(o)));
+    end loop;
+
+    info("m_O read!");
+
+    wait until rising_edge(clk);
+    saved <= true;
+    wait;
+  end process;
+
+--
+
+  uut_vc: entity work.tb_vc_axis_loop
+    generic map (
+      m_axis => m_axis,
+      s_axis => s_axis,
+      data_width => data_width,
+      fifo_depth => fifo_depth
+    )
+    port map (
+      clk  => clk,
+      rstn => rstn
+    );
+
+end architecture;
diff --git a/examples/vhdl/array_axis_vcs/src/test/tb_py_axis_loop.vhd b/examples/vhdl/array_axis_vcs/src/test/tb_py_axis_loop.vhd
@@ -32,7 +32,7 @@ architecture tb of tb_py_axis_loop is
 
   -- Simulation constants
 
-  constant clk_period : time := 20 ns;
+  constant clk_period : time    := 20 ns;
   constant data_width : natural := 32;
 
   -- AXI4Stream Verification Components
@@ -42,8 +42,8 @@ architecture tb of tb_py_axis_loop is
 
   -- tb signals and variables
 
-  signal clk, rst, rstn : std_logic := '0';
-  signal start, sent, saved : boolean := false;
+  signal clk, rst, rstn     : std_logic := '0';
+  signal start, sent, saved : boolean   := false;
   shared variable m_I, m_O : array_t;
 
 begin
diff --git a/examples/vhdl/array_axis_vcs/src/test/tb_vc_axis_loop.vhd b/examples/vhdl/array_axis_vcs/src/test/tb_vc_axis_loop.vhd
@@ -1,3 +1,9 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2019, Lars Asplund lars.anders.asplund@gmail.com
+
 library ieee;
 context ieee.ieee_std_context;
 
diff --git a/vunit/test/acceptance/test_external_run_scripts.py b/vunit/test/acceptance/test_external_run_scripts.py
@@ -16,7 +16,7 @@
 import sys
 from vunit import ROOT
 from vunit.builtins import VHDL_PATH
-from vunit.test.common import has_simulator, check_report, simulator_is
+from vunit.test.common import has_simulator, check_report, simulator_is, simulator_check
 
 
 def simulator_supports_verilog():
@@ -109,6 +109,10 @@ def test_vhdl_json4vhdl_example_project(self):
     def test_vhdl_array_example_project(self):
         self.check(join(ROOT, "examples", "vhdl", "array", "run.py"))
 
+    @unittest.skipIf(
+        simulator_check(lambda simclass: not simclass.supports_vhpi()),
+        "This simulator/backend does not support interfacing with external C code"
+    )
     def test_vhdl_array_axis_vcs_example_project(self):
         self.check(join(ROOT, "examples", "vhdl", "array_axis_vcs", "run.py"))
 
