Added support for manual addition of VHDL configurations.

Author: LarsAsplund

tests/acceptance/artificial/vhdl/cfg1.vhd

@@ -0,0 +1,18 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2023, Lars Asplund lars.anders.asplund@gmail.com
+
+architecture arch1 of ent is
+begin
+  arch <= "arch1";
+end;
+
+configuration cfg1 of tb_with_vhdl_configuration is
+  for tb
+    for ent_inst : ent
+      use entity work.ent(arch1);
+    end for;
+  end for;
+end;

tests/acceptance/artificial/vhdl/cfg2.vhd

@@ -0,0 +1,18 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2023, Lars Asplund lars.anders.asplund@gmail.com
+
+architecture arch2 of ent is
+begin
+  arch <= "arch2";
+end;
+
+configuration cfg2 of tb_with_vhdl_configuration is
+  for tb
+    for ent_inst : ent
+      use entity work.ent(arch2);
+    end for;
+  end for;
+end;

tests/acceptance/artificial/vhdl/ent.vhd

@@ -0,0 +1,9 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2023, Lars Asplund lars.anders.asplund@gmail.com
+
+entity ent is
+  port(arch : out string(1 to 5));
+end;

tests/acceptance/artificial/vhdl/run.py

@@ -94,10 +94,27 @@ def configure_tb_assert_stop_level(ui):
             test.set_sim_option("vhdl_assert_stop_level", vhdl_assert_stop_level)
 
 
+def configure_tb_with_vhdl_configuration(ui):
+    def make_post_check(expected_arch):
+        def post_check(output_path):
+            arch = (Path(output_path) / "result.txt").read_text()
+            if arch[:-1] != expected_arch:
+                raise RuntimeError(f"Error! Got {arch[: -1]}, expected {expected_arch}")
+
+            return True
+
+        return post_check
+
+    tb = ui.library("lib").entity("tb_with_vhdl_configuration")
+    tb.add_config(name="cfg1", post_check=make_post_check("arch1"), vhdl_configuration_name="cfg1")
+    tb.add_config(name="cfg2", post_check=make_post_check("arch2"), vhdl_configuration_name="cfg2")
+
+
 configure_tb_with_generic_config()
 configure_tb_same_sim_all_pass(vu)
 configure_tb_set_generic(vu)
 configure_tb_assert_stop_level(vu)
+configure_tb_with_vhdl_configuration(vu)
 lib.entity("tb_no_generic_override").set_generic("g_val", False)
 lib.entity("tb_ieee_warning").test("pass").set_sim_option("disable_ieee_warnings", True)
 lib.entity("tb_other_file_tests").scan_tests_from_file(str(root / "other_file_tests.vhd"))

tests/acceptance/artificial/vhdl/tb_with_vhdl_configuration.vhd

@@ -0,0 +1,46 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2023, Lars Asplund lars.anders.asplund@gmail.com
+
+library vunit_lib;
+context vunit_lib.vunit_context;
+
+use std.textio.all;
+
+entity tb_with_vhdl_configuration is
+  generic(runner_cfg : string);
+end entity;
+
+architecture tb of tb_with_vhdl_configuration is
+  component ent
+    port(arch : out string(1 to 5));
+  end component;
+
+  signal arch : string(1 to 5);
+
+begin
+  test_runner : process
+    file result_fptr : text;
+    variable result_line : line;
+  begin
+    test_runner_setup(runner, runner_cfg);
+
+    file_open(result_fptr, join(output_path(runner_cfg), "result.txt"), write_mode);
+    write(result_line, arch);
+    writeline(result_fptr, result_line);
+    file_close(result_fptr);
+
+    info(arch);
+
+    test_runner_cleanup(runner);
+    wait;
+  end process;
+
+  ent_inst : ent
+    port map(
+      arch => arch
+    );
+
+end architecture;

tests/acceptance/test_artificial.py

@@ -245,4 +245,12 @@ def test_exit_0_flag(self):
         "failed",
         "lib.tb_assert_stop_level.Report failure when VHDL assert stop level = failure",
     ),
+    (
+        "passed",
+        "lib.tb_with_vhdl_configuration.cfg1",
+    ),
+    (
+        "passed",
+        "lib.tb_with_vhdl_configuration.cfg2",
+    ),
 )

tests/unit/test_incisive_interface.py

@@ -21,6 +21,8 @@
 from vunit.ostools import renew_path, write_file, read_file
 from vunit.test.bench import Configuration
 from vunit.vhdl_standard import VHDL
+from tests.common import create_tempdir
+from tests.unit.test_test_bench import Entity
 
 
 class TestIncisiveInterface(unittest.TestCase):
@@ -956,6 +958,21 @@ def test_simulate_gui(self, run_command, find_cds_root_irun, find_cds_root_virtu
             ],
         )
 
+    @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_virtuoso")
+    @mock.patch("vunit.sim_if.incisive.IncisiveInterface.find_cds_root_irun")
+    def test_configuration_and_entity_selection(self, find_cds_root_irun, find_cds_root_virtuoso):
+        find_cds_root_irun.return_value = "cds_root_irun"
+        find_cds_root_virtuoso.return_value = None
+
+        with create_tempdir() as tempdir:
+            design_unit = Entity("tb_entity", file_name=str(Path(tempdir) / "file.vhd"))
+            design_unit.generic_names = ["runner_cfg"]
+            config = Configuration("name", design_unit, vhdl_configuration_name="cfg")
+            simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
+            self.assertEqual(simif._select_vhdl_top(config), "cfg")  # pylint: disable=protected-access
+            config = Configuration("name", design_unit)
+            self.assertEqual(simif._select_vhdl_top(config), "lib.tb_entity:arch")  # pylint: disable=protected-access
+
     def setUp(self):
         self.output_path = str(Path(__file__).parent / "test_incisive_out")
         renew_path(self.output_path)
@@ -985,4 +1002,5 @@ def make_config(sim_options=None, generics=None, verilog=False):
 
     cfg.sim_options = {} if sim_options is None else sim_options
     cfg.generics = {} if generics is None else generics
+    cfg.vhdl_configuration_name = None
     return cfg

vunit/configuration.py

@@ -39,12 +39,14 @@ def __init__(  # pylint: disable=too-many-arguments
         pre_config=None,
         post_check=None,
         attributes=None,
+        vhdl_configuration_name=None,
     ):
         self.name = name
         self._design_unit = design_unit
         self.generics = {} if generics is None else generics
         self.sim_options = {} if sim_options is None else sim_options
         self.attributes = {} if attributes is None else attributes
+        self.vhdl_configuration_name = vhdl_configuration_name
 
         self.tb_path = str(Path(design_unit.original_file_name).parent)
 
@@ -64,6 +66,7 @@ def copy(self):
             pre_config=self.pre_config,
             post_check=self.post_check,
             attributes=self.attributes.copy(),
+            vhdl_configuration_name=self.vhdl_configuration_name,
         )
 
     @property
@@ -102,6 +105,12 @@ def set_attribute(self, name, value):
         else:
             raise AttributeException
 
+    def set_vhdl_configuration_name(self, name):
+        """
+        Set VHDL configuration name
+        """
+        self.vhdl_configuration_name = name
+
     def set_generic(self, name, value):
         """
         Set generic
@@ -248,6 +257,7 @@ def add_config(  # pylint: disable=too-many-arguments
         post_check=None,
         sim_options=None,
         attributes=None,
+        vhdl_configuration_name=None,
     ):
         """
         Add a configuration copying unset fields from the default configuration:
@@ -283,4 +293,7 @@ def add_config(  # pylint: disable=too-many-arguments
                         raise AttributeException
                 config.attributes.update(attributes)
 
+            if vhdl_configuration_name is not None:
+                config.vhdl_configuration_name = vhdl_configuration_name
+
             configs[config.name] = config

vunit/sim_if/activehdl.py

@@ -239,11 +239,14 @@ def _create_load_function(self, config, output_path):
             set_generic_name_str,
             "-lib",
             config.library_name,
-            config.entity_name,
         ]
 
-        if config.architecture_name is not None:
-            vsim_flags.append(config.architecture_name)
+        if config.vhdl_configuration_name is None:
+            vsim_flags.append(config.entity_name)
+            if config.architecture_name is not None:
+                vsim_flags.append(config.architecture_name)
+        else:
+            vsim_flags.append(config.vhdl_configuration_name)
 
         if config.sim_options.get("enable_coverage", False):
             coverage_file_path = str(Path(output_path) / "coverage.acdb")

vunit/sim_if/ghdl.py

@@ -279,7 +279,11 @@ def _get_command(self, config, output_path, elaborate_only, ghdl_e, wave_file):
         if config.sim_options.get("enable_coverage", False):
             # Enable coverage in linker
             cmd += ["-Wl,-lgcov"]
-        cmd += [config.entity_name, config.architecture_name]
+
+        if config.vhdl_configuration_name is not None:
+            cmd += [config.vhdl_configuration_name]
+        else:
+            cmd += [config.entity_name, config.architecture_name]
 
         sim = config.sim_options.get("ghdl.sim_flags", [])
         for name, value in config.generics.items():