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fix(examples/vhdl/array_axis_vcs): set objec(s) for one of the
testbenches only
1 parent 752415e commit aee9b4b

1 file changed

Lines changed: 2 additions & 2 deletions

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  • examples/vhdl/array_axis_vcs

examples/vhdl/array_axis_vcs/run.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,9 @@
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# vu.set_sim_option('modelsim.init_files.after_load',['runall_addwave.do'])
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c_obj = join(root, 'src', 'test', 'main.o')
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print(os.popen('gcc -fPIC -rdynamic -c '+join(root, 'src/**/*.c')+' -o '+c_obj).read())
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vu.set_objects([c_obj])
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for tb in lib.get_test_benches(pattern='*tb_c_*', allow_empty=False):
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tb.set_sim_options.get('ghdl.elab_flags', ["-Wl," + " ".join([c_obj])], overwrite=False)
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vu.main()

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