style(examples/vhdl/array_axis_vcs): avoid using protected shared variables

Author: umarcor

examples/vhdl/array_axis_vcs/run.py

@@ -23,7 +23,7 @@
 # vu.set_sim_option('modelsim.init_files.after_load',['runall_addwave.do'])
 
 c_obj = join(root, 'src', 'test', 'main.o')
-print(os.popen('gcc -fPIC -rdynamic -c '+join(root, 'src/**/*.c')+' -o '+c_obj).read())
+print(os.popen('gcc -fPIC -rdynamic -c '+join(root, 'src/**/main.c')+' -o '+c_obj).read())
 
 for tb in lib.get_test_benches(pattern='*tb_c_*', allow_empty=False):
     tb.set_sim_options.get('ghdl.elab_flags', ["-Wl," + " ".join([c_obj])], overwrite=False)

examples/vhdl/array_axis_vcs/src/test/pkg_c.vhd

@@ -10,42 +10,49 @@ package pkg_c is
     attribute foreign of get_param :
       function is "VHPIDIRECT get_param";
 
-  constant stream_length : integer := get_param(0);
-
-  type buffer_t is array(integer range 0 to stream_length-1) of integer;
+  --integer'high is 2147483647, but the limit here seems to be 128 times less. Otherwise, it fails.
+  constant max_length: integer:= 16777215;
+  type buffer_t is array(integer range 0 to max_length) of integer;
   type buffer_p is access buffer_t;
 
   impure function get_addr(f: integer) return buffer_p;
     attribute foreign of get_addr :
       function is "VHPIDIRECT get_addr";
 
-  type buffet_t_prot is protected
-    procedure init ( i: integer );
-    procedure set ( i: integer; v: integer);
-    impure function get (i: integer) return integer;
-  end protected buffet_t_prot;
+  type memory_t is record
+    -- Private
+    p_id: integer;
+  end record;
+
+  impure function new_memory(id: integer := -1) return memory_t;
+  procedure write_word ( memory: memory_t; i, v: integer );
+  impure function read_word ( memory: memory_t; i: integer ) return integer;
 
 end pkg_c;
 
 package body pkg_c is
   function get_param(f: integer) return integer is begin
     assert false report "VHPI" severity failure;
-  end get_param;
+  end function;
 
   impure function get_addr(f: integer) return buffer_p is begin
     assert false report "VHPI" severity failure;
-  end get_addr;
-
-  type buffet_t_prot is protected body
-    variable var: buffer_p;
-    procedure init ( i: integer ) is begin
-      var := get_addr(i);
-    end procedure;
-    procedure set ( i: integer; v: integer ) is begin
-      var(i) := v;
-    end procedure;
-    impure function get ( i: integer ) return integer is begin
-      return var(i);
-    end get;
-  end protected body buffet_t_prot;
+  end function;
+
+  impure function new_memory(id: integer := -1) return memory_t is begin
+    return (p_id => id);
+  end;
+
+  procedure write_word ( memory: memory_t; i, v: integer ) is
+    variable buf: buffer_p := get_addr(memory.p_id);
+  begin
+    buf(i) := v;
+  end procedure;
+
+  impure function read_word ( memory: memory_t; i: integer ) return integer is
+    variable buf: buffer_p := get_addr(memory.p_id);
+  begin
+    return buf(i);
+  end function;
+
 end pkg_c;

examples/vhdl/array_axis_vcs/src/test/tb_c_axis_loop.vhd

@@ -18,6 +18,7 @@ library vunit_lib;
 context vunit_lib.vunit_context;
 context vunit_lib.vc_context;
 
+use work.pkg_c;
 use work.pkg_c.all;
 
 entity tb_c_axis_loop is
@@ -30,20 +31,23 @@ end entity;
 architecture tb of tb_c_axis_loop is
   -- Simulation constants
 
-  constant clk_period : time    := 20 ns;
-  constant data_width : natural := get_param(1);
-  constant fifo_depth : natural := get_param(2);
+  constant clk_period    : time    := 20 ns;
+  constant stream_length : integer := get_param(0);
+  constant data_width    : natural := get_param(1);
+  constant fifo_depth    : natural := get_param(2);
 
   -- AXI4Stream Verification Components
 
   constant m_axis : axi_stream_master_t := new_axi_stream_master(data_length => data_width);
   constant s_axis : axi_stream_slave_t := new_axi_stream_slave(data_length => data_width);
 
+  constant ibuffer: pkg_c.memory_t := pkg_c.new_memory(0);
+  constant obuffer: pkg_c.memory_t := pkg_c.new_memory(1);
+
   -- tb signals and variables
 
   signal clk, rst, rstn     : std_logic := '0';
   signal start, sent, saved : boolean   := false;
-  shared variable ibuffer, obuffer: buffet_t_prot;
 
 begin
 
@@ -62,8 +66,6 @@ begin
     test_runner_setup(runner, runner_cfg);
     while test_suite loop
       if run("test") then
-        ibuffer.init(0);
-        obuffer.init(1);
         rst <= '1';
         wait for 15*clk_period;
         rst <= '0';
@@ -84,7 +86,7 @@ begin
 
     for y in 0 to stream_length-1 loop
       wait until rising_edge(clk);
-      push_axi_stream(net, m_axis, std_logic_vector(to_signed(ibuffer.get(y), data_width)) , tlast => '0');
+      push_axi_stream(net, m_axis, std_logic_vector(to_signed(pkg_c.read_word(ibuffer, y), data_width)) , tlast => '0');
     end loop;
 
     info("m_I sent!");
@@ -104,7 +106,7 @@ begin
 
     for y in 0 to stream_length-1 loop
       pop_axi_stream(net, s_axis, tdata => o, tlast => last);
-      obuffer.set(y,to_integer(signed(o)));
+      pkg_c.write_word(obuffer, y, to_integer(signed(o)));
     end loop;
 
     info("m_O read!");