Add Cadence Xcelium support

tests/acceptance/test_artificial.py

@@ -27,7 +27,7 @@ class TestVunitArtificial(unittest.TestCase):
     """
 
     def setUp(self):
-        if simulator_is("activehdl"):
+        if simulator_is("activehdl", "incisive", "xcelium"):
             self.output_path = str(ROOT / "artificial_out")
         else:
             # Spaces in path intentional to verify that it is supported

tools/xcelium_verilog_fixup.py

@@ -0,0 +1,59 @@
+# This Source Code Form is subject to the terms of the Mozilla Public
+# License, v. 2.0. If a copy of the MPL was not distributed with this file,
+# You can obtain one at http://mozilla.org/MPL/2.0/.
+#
+# Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com
+
+"""
+Perform necessary modifications to VUnit Verilog code to support
+Cadence Xcelium
+"""
+
+import os
+import re
+from pathlib import Path
+
+
+def replace_stop_by_finish(file_name):
+    """
+    Replace $stop by $finish
+    """
+
+    with Path(file_name).open("r", encoding="iso-8859-1") as fptr:
+        text = fptr.read()
+
+    text = text.replace("$stop(", "$finish(")
+
+    with Path(file_name).open("w", encoding="iso-8859-1") as fptr:
+        fptr.write(text)
+
+
+def add_finish_after_error(file_name):
+    """
+    Add $finish after a $error
+    """
+
+    with Path(file_name).open("r", encoding="iso-8859-1") as fptr:
+        text = fptr.read()
+
+    text = re.sub(r"(\$error\(.*\))", "\\1; $finish(1)", text)
+
+    with Path(file_name).open("w", encoding="iso-8859-1") as fptr:
+        fptr.write(text)
+
+
+def main():
+    """
+    Remove xcelium incompatabilities from source code
+    """
+    where = "../vunit/verilog"
+    root = os.path.abspath(os.path.join(os.path.dirname(__file__), where))
+    for base, _, files in os.walk(root):
+        for file_name in files:
+            if file_name.endswith(".sv") or file_name.endswith(".svh"):
+                replace_stop_by_finish(os.path.join(base, file_name))
+                add_finish_after_error(os.path.join(base, file_name))
+
+
+if __name__ == "__main__":
+    main()

vunit/sim_if/cds_file.py

@@ -5,7 +5,7 @@
 # Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com
 
 """
-Handles Cadence Incisive .cds files
+Handles Cadence Incisive/Xcelium .cds files
 """
 
 import re
@@ -14,7 +14,7 @@
 
 class CDSFile(dict):
     """
-    Handles Cadence Incisive .cds files
+    Handles Cadence Incisive/Xcelium .cds files
 
     Only cares about 'define' but other lines are kept intact
     """

vunit/sim_if/factory.py

@@ -11,6 +11,7 @@
 import os
 from .activehdl import ActiveHDLInterface
 from .ghdl import GHDLInterface
+from .xcelium import XceliumInterface
 from .incisive import IncisiveInterface
 from .modelsim import ModelSimInterface
 from .rivierapro import RivieraProInterface
@@ -32,6 +33,7 @@ def supported_simulators():
             RivieraProInterface,
             ActiveHDLInterface,
             GHDLInterface,
+            XceliumInterface,
             IncisiveInterface,
         ]
 

vunit/sim_if/incisive.py

@@ -40,24 +40,7 @@ class IncisiveInterface(  # pylint: disable=too-many-instance-attributes
 
     sim_options = [ListOfStringOption("incisive.irun_sim_flags")]
 
-    @staticmethod
-    def add_arguments(parser):
-        """
-        Add command line arguments
-        """
-        group = parser.add_argument_group(
-            "Incisive irun", description="Incisive irun-specific flags"
-        )
-        group.add_argument(
-            "--cdslib",
-            default=None,
-            help="The cds.lib file to use. If not given, VUnit maintains its own cds.lib file.",
-        )
-        group.add_argument(
-            "--hdlvar",
-            default=None,
-            help="The hdl.var file to use. If not given, VUnit does not use a hdl.var file.",
-        )
+    # NOTE: Incisive shares the command-line arguments with Xcelium
 
     @classmethod
     def from_args(cls, args, output_path, **kwargs):