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plafosseplafosse
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Ensure rounding flag is properly emitted on some x86 floating point instructions
1 parent 2678767 commit 508ba2b

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3 files changed

+18
-14
lines changed

3 files changed

+18
-14
lines changed

‎arch/x86/arch_x86.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2152,6 +2152,10 @@ size_t X86CommonArchitecture::GetFlagWriteLowLevelIL(BNLowLevelILOperation op, s
21522152
break;
21532153
}
21542154
}
2155+
2156+
if (flagWriteType == IL_FLAGWRITE_X87RND && flag == IL_FLAG_C1)
2157+
return il.Undefined();
2158+
21552159
if (((flagWriteType == IL_FLAGWRITE_X87COM) || (flagWriteType == IL_FLAGWRITE_X87C1Z)) && (flag == IL_FLAG_C1))
21562160
return il.Const(0, 0);
21572161
return Architecture::GetFlagWriteLowLevelIL(op, size, flagWriteType, flag, operands, operandCount, il);

‎arch/x86/arch_x86_intrinsics.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5183,9 +5183,9 @@ vector<NameAndType> X86CommonArchitecture::GetIntrinsicInputs(uint32_t intrinsic
51835183

51845184
vector<Confidence<Ref<Type>>> X86CommonArchitecture::GetIntrinsicOutputs(uint32_t intrinsic)
51855185
{
5186-
static const vector<Confidence<Ref<Type>>> singleFloat10 { Type::FloatType(10)->SetIgnored(true) };
5186+
static const vector<Confidence<Ref<Type>>> singleFloat10Bool { Type::FloatType(10)->SetIgnored(true), Type::BoolType()->SetIgnored(true) };
51875187
static const vector<Confidence<Ref<Type>>> singleInt10 { Type::IntegerType(10, false)->SetIgnored(true) };
5188-
static const vector<Confidence<Ref<Type>>> float10Bool { Type::FloatType(10)->SetIgnored(true), Type::BoolType()->SetIgnored(true) };
5188+
static const vector<Confidence<Ref<Type>>> float10BoolBool { Type::FloatType(10)->SetIgnored(true), Type::BoolType()->SetIgnored(true), Type::BoolType()->SetIgnored(true) };
51895189
static const vector<Confidence<Ref<Type>>> doubleFloat10Bool { Type::FloatType(10)->SetIgnored(true), Type::FloatType(10)->SetIgnored(true), Type::BoolType()->SetIgnored(true) };
51905190
static const vector<Confidence<Ref<Type>>> float10BoolInt1 { Type::FloatType(10)->SetIgnored(true), Type::BoolType()->SetIgnored(true), Type::IntegerType(1, false)->SetIgnored(true) };
51915191
static const vector<Confidence<Ref<Type>>> quadBool { Type::BoolType()->SetIgnored(true), Type::BoolType()->SetIgnored(true), Type::BoolType()->SetIgnored(true), Type::BoolType()->SetIgnored(true) };
@@ -5202,13 +5202,13 @@ vector<Confidence<Ref<Type>>> X86CommonArchitecture::GetIntrinsicOutputs(uint32_
52025202
case INTRINSIC_FSCALE:
52035203
case INTRINSIC_FYL2X:
52045204
case INTRINSIC_FYL2XP1:
5205-
return singleFloat10;
5205+
return singleFloat10Bool;
52065206
case INTRINSIC_FBST:
52075207
return singleInt10;
52085208
case INTRINSIC_FSIN:
52095209
case INTRINSIC_FCOS:
52105210
case INTRINSIC_FPTAN:
5211-
return float10Bool;
5211+
return float10BoolBool;
52125212
case INTRINSIC_FSINCOS:
52135213
return doubleFloat10Bool;
52145214
case INTRINSIC_FPREM:

‎arch/x86/il.cpp‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4742,13 +4742,13 @@ bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLev
47424742
break;
47434743

47444744
case XED_ICLASS_F2XM1:
4745-
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0) },
4745+
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), RegisterOrFlag::Flag(IL_FLAG_C1)},
47464746
INTRINSIC_F2XM1, vector<ExprId> { il.Register(10, XED_REG_ST0) }, IL_FLAGWRITE_X87RND));
47474747
break;
47484748

47494749
case XED_ICLASS_FBLD:
47504750
il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Sub(2, il.Register(2, REG_X87_TOP), il.Const(2, 1))));
4751-
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0) },
4751+
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), RegisterOrFlag::Flag(IL_FLAG_C1) },
47524752
INTRINSIC_FBLD, vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) }, IL_FLAGWRITE_X87C1Z));
47534753
break;
47544754

@@ -4764,25 +4764,25 @@ bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLev
47644764

47654765
case XED_ICLASS_FSIN:
47664766
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0),
4767-
RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FSIN, vector<ExprId> { il.Register(10, XED_REG_ST0) },
4767+
RegisterOrFlag::Flag(IL_FLAG_C1), RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FSIN, vector<ExprId> { il.Register(10, XED_REG_ST0) },
47684768
IL_FLAGWRITE_X87RND));
47694769
break;
47704770

47714771
case XED_ICLASS_FCOS:
47724772
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0),
4773-
RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FCOS, vector<ExprId> { il.Register(10, XED_REG_ST0) },
4773+
RegisterOrFlag::Flag(IL_FLAG_C1), RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FCOS, vector<ExprId> { il.Register(10, XED_REG_ST0) },
47744774
IL_FLAGWRITE_X87RND));
47754775
break;
47764776

47774777
case XED_ICLASS_FSINCOS:
47784778
il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Sub(2, il.Register(2, REG_X87_TOP), il.Const(2, 1))));
47794779
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1),
4780-
RegisterOrFlag::Register(XED_REG_ST0), RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FSINCOS,
4780+
RegisterOrFlag::Register(XED_REG_ST0), RegisterOrFlag::Flag(IL_FLAG_C1), RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FSINCOS,
47814781
vector<ExprId> { il.Register(10, XED_REG_ST1) }, IL_FLAGWRITE_X87RND));
47824782
break;
47834783

47844784
case XED_ICLASS_FPATAN:
4785-
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1) },
4785+
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1), RegisterOrFlag::Flag(IL_FLAG_C1) },
47864786
INTRINSIC_FPATAN, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) }, IL_FLAGWRITE_X87RND));
47874787
il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0));
47884788
il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1))));
@@ -4822,7 +4822,7 @@ bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLev
48224822

48234823
case XED_ICLASS_FPTAN:
48244824
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0),
4825-
RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FPTAN, vector<ExprId> { il.Register(10, XED_REG_ST0) },
4825+
RegisterOrFlag::Flag(IL_FLAG_C1), RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FPTAN, vector<ExprId> { il.Register(10, XED_REG_ST0) },
48264826
IL_FLAGWRITE_X87RND));
48274827
il.AddInstruction(il.If(il.Flag(IL_FLAG_C2), doneLabel, falseLabel));
48284828
il.MarkLabel(falseLabel);
@@ -4836,7 +4836,7 @@ bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLev
48364836
break;
48374837

48384838
case XED_ICLASS_FSCALE:
4839-
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0) },
4839+
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), RegisterOrFlag::Flag(IL_FLAG_C1) },
48404840
INTRINSIC_FSCALE, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) },
48414841
IL_FLAGWRITE_X87RND));
48424842
break;
@@ -4855,15 +4855,15 @@ bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLev
48554855
break;
48564856

48574857
case XED_ICLASS_FYL2X:
4858-
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1) },
4858+
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1), RegisterOrFlag::Flag(IL_FLAG_C1)},
48594859
INTRINSIC_FYL2X, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) },
48604860
IL_FLAGWRITE_X87RND));
48614861
il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0));
48624862
il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1))));
48634863
break;
48644864

48654865
case XED_ICLASS_FYL2XP1:
4866-
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1) },
4866+
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1), RegisterOrFlag::Flag(IL_FLAG_C1)},
48674867
INTRINSIC_FYL2XP1, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) },
48684868
IL_FLAGWRITE_X87RND));
48694869
il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0));

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