[arch/x86] Intel APX support

[nullableVoidPtr]

• EGPRs
• JMPABS
• Push/Pop
  • PUSH2
  • PUSHP
  • POP2
  • POPP
• CCMPSCC
• CFCMOVCC
• CTESTSCC
• SETCC
• Zero Upper
  • IMUL
  • SETCC
• New Data Destination

Resolves #5246

[xusheng6]

@nullableVoidPtr thx for your work! Please let me know when you think the code is ready for reviewer!

[emesare]

The push / pop lifting looks fine on the binary https://github.com/user-attachments/files/23866882/apxbin.zip

[emesare]

CCMP also looks correct, the conditional CMP block and the DFV write block look fine.

[nullableVoidPtr]

Thanks for the test bin - I'll be sure to test against that; do you have a corpus for the other extension instructions?

[stong]

👏

[emesare]

Thanks for the test bin - I'll be sure to test against that; do you have a corpus for the other extension instructions?

I do not, I will make another with more of the extensions instructions expressed, thank you for responding quick!

[nullableVoidPtr]

Heya, I consider this extension complete - is there any other blockers besides your testing?

[emesare]

Heya, I consider this extension complete - is there any other blockers besides your testing?

None, just have not merged it yet, will get it done shortly, sorry!

[emesare]

The sizing of non-ndd instructions was messed up between commits, I am running tests on the branch below, if you could double check my changes, once im done what I will do is merge my changes into your branch and then squash with you as the author

ab9dd3f

[nullableVoidPtr]

Good catch with the NDD op lens, LGTM

[emesare]

Okay testing is done, I checked this branch against ~200k object files and nothing changed (which is good!), no performance regressions either, however I did find a blind spot in our COFF relocations in one binary leading to a fall through of a no-return call that then disassembles as an NDD instruction, but that is a separate issue entirely 😆.

[emesare]

Available in 5.3.9178 thank you!